Cypress CY7C1418AV18 Pin Configuration, Ball Fbga 15 x 17 x 1.4 mm Pinout, CY7C1416AV18 4M x

Page 4

CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Pin Configuration

The pin configuration for CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 follow. [1]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1416AV18 (4M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

CQ

R/W

NWS1

K

NC/144M

LD

A

A

CQ

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

DQ3

NWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

D

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ4

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

NC

DQ5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ1

NC

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

DQ6

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

N

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ7

A

A

C

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1427AV18 (4M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC

NC/144M

A

A

CQ

CQ

R/W

K

LD

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

DQ3

BWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

D

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ4

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

NC

DQ5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ1

NC

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

DQ6

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

N

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ7

A

A

C

A

A

NC

NC

DQ8

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Note

1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 38-05616 Rev. *F

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1416AV18 Logic Block Diagram CY7C1427AV18Doff CLKLogic Block Diagram CY7C1420AV18 Logic Block Diagram CY7C1418AV18BWS Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1416AV18 4M x CY7C1427AV18 4M xCY7C1418AV18 2M x CY7C1420AV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read or Write Input. When Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Application Example Depth ExpansionProgrammable Impedance Echo ClocksBWS0 BWS1 Write Cycle DescriptionsNWS0 NWS1 BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Clock Rise or K/K in single Clock mode to Data Valid Switching Waveforms NOPRead NOP Write ReadOrdering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmECN Document HistoryOirg. Submission Date Description Of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsVKN/AESA Pyrs