Pin Definitions, Pin Name Pin Description

CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Pin Definitions

Pin Name

Pin Description

DQ[x:0]

Input Output-

Data Input Output Signals. Inputs are sampled on the rising edge of K and

clocks during valid write

Synchronous

operations. These pins drive out the requested data during a read operation. Valid data is driven out on

the rising edge of both the C and C clocks during read operations or K and K when in single clock mode.

When read access is deselected, Q[x:0] are automatically tri-stated.

CY7C1416AV18 − DQ[7:0]

CY7C1427AV18 − DQ[8:0]

CY7C1418AV18 − DQ[17:0]

CY7C1420AV18 − DQ[35:0]

Input-

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition

Synchronous

includes address and read/write direction. All transactions operate on a burst of 2 data. LD must meet

the setup and hold times around edge of K.

NWS

Input-

Nibble Write Select 0, 1 − Active LOW (CY7C1416AV18 only). Sampled on the rising edge of the K

NWS1

Synchronous

and K clocks during write operations. Used to select which nibble is written into the device during the

current portion of the write operations. Nibbles not written remain unaltered.

NWS0 controls D[3:0] and NWS1 controls D[7:4].

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device.

BWS

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and

clocks during

BWS1,

Synchronous

write operations. Used to select which byte is written into the device during the current portion of the write

operations. Bytes not written remain unaltered.

BWS2,

CY7C1427AV18 − BWS controls D

BWS3

CY7C1418AV18 − BWS00 controls D[8:0][8:0]

and

1 controls D

[17:9].

BWS

CY7C1420AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3 controls

D[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A, A0

Input-

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the

Synchronous

device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1416AV18, 4M x 9 (2 arrays each of

2M x 9) for CY7C1427AV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1418AV18, and 1M x 36 (2

arrays each of 512K x 36) for CY7C1420AV18.

CY7C1416AV18 – Since the least significant bit of the address internally is a “0,” only 21 external address

inputs are needed to access the entire memory array.

CY7C1427AV18 – Since the least significant bit of the address internally is a “0,” only 21 external address

inputs are needed to access the entire memory array.

CY7C1418AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.

21 address inputs are needed to access the entire memory array.

CY7C1420AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.

20 address inputs are needed to access the entire memory array. All the address inputs are ignored when

the appropriate port is deselected.

R/W

Input-

Synchronous Read or Write Input. When

is LOW, this input designates the access type (read when

Synchronous

R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times

around edge of K.

CInput Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. Use the C and C together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 9 for further details.

CInput Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. Use the C and C together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 9 for further details.

K	Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
	and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
	edge of K.

KInput Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0] when in single clock mode.

Document Number: 38-05616 Rev. *F

Page 6 of 31

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