Cypress CY7C1420AV18 manual Document History, Ecn, Oirg. Submission Date Description Of Change

Page 30

CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Document History Page

Document Title: CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, CY7C1420AV18, 36-Mbit DDR-II SRAM 2-Word Burst

Architecture

Document Number: 38-05616

Rev.

ECN

Oirg. Of

Submission Date

Description Of Change

Change

 

 

 

 

 

 

 

 

 

**

247331

SYT

08/26/04

New Data Sheet

 

 

 

 

 

*A

326519

SYT

04/14/05

Removed CY7C1420AV18 from the title

 

 

 

 

Included 300 MHz Speed grade

 

 

 

 

Replaced TBDs with their respective values for IDD and ISB1

 

 

 

 

Added Industrial temperature grade

 

 

 

 

Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 17.2°C/W

 

 

 

 

and ΘJC = 3.2°C/W

 

 

 

 

Replaced TBDs in the Capacitance Table to their respective values for the

 

 

 

 

165 FBGA Package

 

 

 

 

Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS

 

 

 

 

TRI-STATE on Page 18

 

 

 

 

Added lead-free Product Information

 

 

 

 

Updated the Ordering Information by Shading and Unshading MPNs as per

 

 

 

 

availability

*B

413953

NXR

12/22/05

Converted from preliminary to final

 

 

 

 

Added CY7C1427AV18 part number to title

 

 

 

 

Added 278-MHz speed Bin

 

 

 

 

Changed C, C Description in Feature Section and Pin Description

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Added Power-up sequence and Wave form on page# 19

 

 

 

 

Added Footnotes# 13, 14, 15 on page# 19

 

 

 

 

Replaced Three-state with Tri-state

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

Current on page# 20

 

 

 

 

Modified the IDD and ISB values

 

 

 

 

Modified test condition in Footnote #17 on page# 20 from VDDQ < VDD to

 

 

 

 

VDDQ < VDD

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table.

 

 

 

 

Updated Ordering Information Table

*C

468029

NXR

07/10/06

Modified the ZQ Definition from Alternately, this pin can be connected

 

 

 

 

directly to VDD to Alternately, this pin can be connected directly to VDDQ

 

 

 

 

Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD

 

 

 

 

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH,

 

 

 

 

tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table

 

 

 

 

Modified Power-Up waveform

 

 

 

 

Changed the Maximum rating of Ambient Temperature with Power Applied

 

 

 

 

from –10°C to +85°C to –55°C to +125°C

 

 

 

 

Added additional notes in the AC parameter section

 

 

 

 

Modified AC Switching Waveform

 

 

 

 

Corrected the typo In the AC Switching Characteristics Table

 

 

 

 

Updated the Ordering Information Table

*D

505682

VKN

12/19/06

Corrected typo in the Functional Description section for burst counter logic

 

 

 

 

 

Document Number: 38-05616 Rev. *F

Page 30 of 31

[+] Feedback

Image 30
Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1416AV18Logic Block Diagram CY7C1427AV18 CLKLogic Block Diagram CY7C1418AV18 Logic Block Diagram CY7C1420AV18BWS CY7C1416AV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1427AV18 4M xCY7C1418AV18 2M x CY7C1420AV18 1M xPin Definitions Pin Name Pin DescriptionSynchronous Read or Write Input. When Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Programmable Impedance Application ExampleDepth Expansion Echo ClocksWrite Cycle Descriptions BWS0 BWS1NWS0 NWS1 BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitSwitching Characteristics Clock Rise or K/K in single Clock mode to Data Valid Read Switching WaveformsNOP NOP Write ReadOrdering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History ECNOirg. Submission Date Description Of Change VKN/AESA Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Pyrs