Cypress CY7C1427AV18 Referenced with Respect to, TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag

Page 7

 

 

 

 

 

 

 

 

 

 

CY7C1416AV18, CY7C1427AV18

 

 

 

 

 

 

 

 

 

 

CY7C1418AV18, CY7C1420AV18

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

 

Pin Description

 

CQ

Output Clock

CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

 

 

 

 

 

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing

 

 

 

 

 

for the echo clocks is shown in the Switching Characteristics on page 23.

 

CQ

 

 

Output Clock

CQ

Referenced with Respect to

C

. This is a free-running clock and is synchronized to the input clock

 

 

 

 

 

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing

 

 

 

 

 

for the echo clocks is shown in the Switching Characteristics on page 23.

 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

 

 

 

 

 

impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

 

 

 

 

 

between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the minimum

 

 

 

 

 

impedance mode. This pin cannot be connected directly to GND or left unconnected.

 

DOFF

 

Input

DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

 

 

 

 

 

in the DLL turned off operation differs from those listed in this data sheet.

 

TDO

Output

TDO for JTAG.

 

 

 

 

 

TCK

Input

TCK Pin for JTAG.

 

TDI

Input

TDI Pin for JTAG.

 

 

 

 

 

TMS

Input

TMS Pin for JTAG.

 

 

 

 

 

NC

N/A

Not Connected to the Die. Tie to any voltage level.

 

NC/72M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

NC/144M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

NC/288M

N/A

Not Connected to the Die. Tie to any voltage level.

 

VREF

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

 

 

 

 

Reference

measurement points.

 

 

 

 

 

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

Ground for the Device.

 

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

Document Number: 38-05616 Rev. *F

Page 7 of 31

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Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1416AV18Logic Block Diagram CY7C1427AV18 DoffLogic Block Diagram CY7C1420AV18 Logic Block Diagram CY7C1418AV18BWS CY7C1427AV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1416AV18 4M xCY7C1420AV18 1M x CY7C1418AV18 2M xPin Name Pin Description Pin DefinitionsSynchronous Read or Write Input. When TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview Echo Clocks Application ExampleDepth Expansion Programmable ImpedanceBWS0 BWS1 Write Cycle DescriptionsNWS0 NWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitSwitching Characteristics Clock Rise or K/K in single Clock mode to Data Valid NOP Write Read Switching WaveformsNOP ReadOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramECN Document HistoryOirg. Submission Date Description Of Change Pyrs Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/AESA