Cypress CY7C1414JV18 TAP Controller Block Diagram, TAP Electrical Characteristics, Tdi, Tck, Tms

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CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18

TAP Controller Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

 

 

 

 

Selection

 

 

 

 

 

 

 

 

 

2

1

0

 

 

 

 

Selection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Register

 

 

 

 

 

 

 

 

 

 

 

 

 

Circuitry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Circuitry

 

 

 

 

 

 

31

 

30

29

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2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

108

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2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Boundary Scan Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAP Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

TAP Electrical Characteristics

Over the Operating Range [10, 11, 12]

Parameter

Description

Test Conditions

Min

Max

Unit

VOH1

Output HIGH Voltage

IOH = 2.0 mA

1.4

 

V

VOH2

Output HIGH Voltage

IOH = 100 μA

1.6

 

V

VOL1

Output LOW Voltage

IOL = 2.0 mA

 

0.4

V

VOL2

Output LOW Voltage

IOL = 100 μA

 

0.2

V

VIH

Input HIGH Voltage

 

0.65VDD

VDD + 0.3

V

VIL

Input LOW Voltage

 

–0.3

0.35VDD

V

IX

Input and Output Load Current

GND VI VDD

–5

5

μA

Notes

10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11.Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5V (Pulse width less than tCYC/2).

12.All Voltage referenced to Ground.

Document #: 001-12561 Rev. *D

Page 15 of 26

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1410JV18 Logic Block Diagram CY7C1425JV18Doff Logic Block Diagram CY7C1414JV18 Logic Block Diagram CY7C1412JV18CY7C1425JV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1410JV18 4M xCY7C1412JV18 2M x WPS BWSCY7C1414JV18 1M x Pin Name Pin Description Pin DefinitionsTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Is Referenced with Respect toFunctional Overview Sram #1 Application ExampleProgrammable Impedance Echo ClocksBWS0 BWS1 Truth TableWrite Cycle Descriptions RPS WPSBWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Waveforms Power Up SequenceElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Test Loads and Waveforms AC Electrical CharacteristicsCapacitance Thermal ResistanceDLL Timing Switching CharacteristicsCypress Consortium Description 267 MHz 250 MHz Unit Parameter Min MaxSwitching Waveforms Write ReadWrite NOP Ordering Information Ball Fbga 15 x 17 x 1.40 mm Package DiagramVKN/AESA REV ECN no Issue ORIG. Description of Change DateDocument History VKN