Cypress CY7C1412JV18, CY7C1410JV18 Capacitance, Thermal Resistance, AC Test Loads and Waveforms

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CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

AC Electrical Characteristics

Over the Operating Range [11]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

V

VIL

Input LOW Voltage

 

VREF – 0.2

V

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V

5

pF

CCLK

Clock Input Capacitance

 

4

pF

CO

Output Capacitance

 

5

pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

165 FBGA

Unit

Package

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard test methods and

17.2

°C/W

 

(Junction to Ambient)

procedures for measuring thermal impedance, in

 

 

 

 

accordance with EIA/JESD51.

 

 

ΘJC

Thermal Resistance

3.2

°C/W

 

 

(Junction to Case)

 

 

 

AC Test Loads and Waveforms

VREF = 0.75V

VREF

 

 

 

 

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

Z0 = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

RQ =

250Ω

(a)

RL = 50Ω

VREF = 0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

 

 

 

 

0.75V

 

 

 

 

 

R = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES[19]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF 0.25V

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Under

ZQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slew Rate = 2 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

RQ =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250Ω

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

19.Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.

Document #: 001-12561 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1410JV18 Logic Block Diagram CY7C1425JV18Doff Logic Block Diagram CY7C1414JV18 Logic Block Diagram CY7C1412JV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1410JV18 4M x CY7C1425JV18 4M xCY7C1412JV18 2M x WPS BWSCY7C1414JV18 1M x Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks Sram #1Write Cycle Descriptions Truth TableRPS WPS BWS0 BWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Waveforms Power Up Sequence in QDR-II SramPower Up Sequence DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Capacitance AC Electrical CharacteristicsThermal Resistance AC Test Loads and WaveformsCypress Consortium Description 267 MHz 250 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingSwitching Waveforms Write ReadWrite NOP Ordering Information Ball Fbga 15 x 17 x 1.40 mm Package DiagramDocument History REV ECN no Issue ORIG. Description of Change DateVKN VKN/AESA