Cypress CY7C1410JV18 manual Logic Block Diagram CY7C1412JV18, Logic Block Diagram CY7C1414JV18

CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

Logic Block Diagram (CY7C1412JV18)

18

D[17:0]

Write	Write
Reg	Reg

20	Address	Add.WriteDecode	1M x 18Array	1M x 18Array
A(19:0)	Gen.
	Register
K	CLK
K

DOFF				Read Data Reg.
	VREF		36		18
		Control
	WPS
		Logic			18
	BWS[1:0]

Read Add. Decode

Reg.

Reg.

Address Register

Control

Logic

Reg.

20 A(19:0)

RPS

C

C

CQ

18 CQ

18 18 Q[17:0]

Logic Block Diagram (CY7C1414JV18)

36

D[35:0]

19Address

A(18:0) Register

K

K CLK

Gen.

DOFF

VREF
		Control
WPS
		Logic
BWS
	[3:0]

	Write		Write
	Reg		Reg
Decode	512K x		512K x	Decode
Write Add.	36 Array		36 Array	Read Add.
	Read Data Reg.
		72	36
					Reg.
			36
					Reg.

Address Register

Control

Logic

Reg.

19 A(18:0)

RPS

C

C

CQ

36 CQ

36 36 Q[35:0]

Document #: 001-12561 Rev. *D Page 3 of 26

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