Cypress CY7C1425JV18, CY7C1410JV18 manual Switching Characteristics, Parameter Min Max, DLL Timing

CY7C1410JV18, CY7C1425JV18

CY7C1412JV18, CY7C1414JV18

Switching Characteristics

Over the Operating Range [19, 20]

Cypress

Consortium

Description

267 MHz

250 MHz

Unit

Parameter

Parameter

Min

Max

Min

Max

t

POWER

V (Typical) to the first access [21]

1

1

ms

DD

tCYC

tKHKH

K Clock and C Clock Cycle Time

3.75

8.4

4.0

8.4

ns

tKH

tKHKL

Input Clock (K/K

and C/C) HIGH

1.5

–

1.6

–

ns

tKL

tKLKH

Input Clock (K/K

and C/C) LOW

1.5

–

1.6

–

ns

tKHKH

tKHKH

K Clock Rise to

Clock Rise and C to

Rise (rising edge to rising edge)

1.68

–

1.8

–

ns

K

C

tKHCH

tKHCH

K/K

Clock Rise to C/C Clock Rise (rising edge to rising edge)

0

1.68

0

1.8

ns

Setup Times

tSA

tAVKH

Address Setup to K Clock Rise

0.3

–

0.35

–

ns

tSC

tIVKH

Control Setup to K Clock Rise

0.3

–

0.35

–

ns

(RPS,

WPS)

tSCDDR

tIVKH

DDR Control Setup to Clock (K/K)

Rise (BWS0, BWS1, BWS3, BWS4)

0.3

–

0.35

–

ns

tSD

tDVKH

Rise

0.3

–

0.35

–

ns

D[X:0] Setup to Clock (K/K)

Hold Times

tHA

tKHAX

Address Hold after K Clock Rise

0.3

–

0.35

–

ns

tHC

tKHIX

Control Hold after K Clock Rise

0.3

–

0.35

–

ns

(RPS,

WPS)

tHCDDR

tKHIX

Rise

0,

1,

3

4)

0.3

–

0.35

–

ns

DDR Control Hold after Clock (K/K)

(BWS

BWS

BWS

,BWS

tHD

tKHDX

Rise

0.3

–

0.35

–

ns

D[X:0] Hold after Clock (K/K)

Output Times

tCO

tCHQV

C/C

Clock Rise (or K/K

in Single Clock Mode) to Data Valid

–

0.45

–

0.45

ns

tDOH

tCHQX

Clock Rise (Active to Active)

–0.45

–

–0.45

–

ns

Data Output Hold after Output C/C

tCCQO

tCHCQV

Clock Rise to Echo Clock Valid

–

0.45

–

0.45

ns

C/C

tCQOH

tCHCQX

Clock Rise

–0.45

–

–0.45

–

ns

Echo Clock Hold after C/C

tCQD

tCQHQV

Echo Clock High to Data Valid

–

0.27

–

0.30

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.27

–

–0.30

–

ns

tCQH

tCQHCQL

HIGH [22]

1.43

–

1.55

–

ns

Output Clock (CQ/CQ)

tCQHCQH

tCQHCQH

CQ Clock Rise to

Clock Rise (rising edge to rising edge) [22]

1.43

–

1.55

–

ns

CQ

tCHZ

tCHQZ

Rise to High-Z (Active to High-Z) [23, 24]

Clock (C/C)

–

0.45

–

0.45

ns

tCLZ

tCHQX1

Rise to Low-Z [23, 24]

Clock (C/C)

–0.45

–

–0.45

–

ns

DLL Timing

tKC Var

tKC Var

Clock Phase Jitter

–

0.20

–

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K, C)

1024

–

1024

–

Cycles

tKC Reset

tKC Reset

K Static to DLL Reset

30

–

30

–

ns

Notes

20.When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

21.This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated.

22.These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.

23.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms on page 21. Transition is measured ± 100 mV from steady state voltage.

24.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Document #: 001-12561 Rev. *D Page 22 of 26

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