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Marvel Group 88F6281 Differential Interface Electrical Characteristics, Clock frequency FCK 100.0

Models: 88F6281

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88F6281

Hardware Specifications

8.7Differential Interface Electrical Characteristics

This section provides the reference clock, AC, and DC characteristics for the following differential interfaces:

PCI Express Interface Electrical Characteristics

SATA Interface Electrical Characteristics

USB Electrical Characteristics

8.7.1Differential Interface Reference Clock Characteristics

8.7.1.1PCI Express Interface Differential Reference Clock Characteristics

Table 64: PCI Express Interface Differential Reference Clock Characteristics

Description	Symbol	Min		Max	Units	Notes
Clock frequency	fCK		100.0		MHz	-
Clock duty cycle	DCrefclk	0.4		0.6	tCK	-
Differential rising/falling slew rate	SRrefclk	0.6		4.0	V/nS	3
Differential high voltage	VIHrefclk	150.0		-	mV	-
Differential low voltage	VILrefclk	-		-150.0	mV	-
Absolute crossing point voltage	Vcross	250.0		550.0	mV	1
Variation of Vcross over all rising clock edges	Vcrs_dlta	-		140.0	mV	1
Average differential clock period accuracy	Tperavg	-300.0		2800.0	ppm	-
Absolute differential clock period	Tperabs	9.8		10.2	nS	2
Differential clock cycle-to-cycle jitter	Tccjit	-		150.0	pS	-

Notes:

General Comment: The reference clock timings are based on 100 ohm test circuit.

General Comment: Refer to the PCI Express Card Electromechanical Specification, Revision 1.1,

March 2005, section 2.1.3 for more information.

1.Defined on a single-ended signal.

2.Including jitter and spread spectrum.

3.Defined from -150 mV to +150 mV on the differential w aveform.

Doc. No. MV-S104859-U0 Rev. E		Copyright © 2008 Marvell
Page 118	Document Classification: Proprietary Information	December 2, 2008, Preliminary

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Marvel Group 88F6281 specifications Differential Interface Electrical Characteristics, Clock frequency FCK 100.0

Contents

Hardware Specifications 88F6281Document Conventions Document Status 88F6281 Hardware SpecificationsDoc Status Preliminary Technical Publication 88F6281 Hardware SpecificationsIntegrated Controller Features High-performance CPU core, running at up toFeatures Supports Ieee 802.1Qav draft Audio Video Bridging networksGbE Port 0 in Gmii mode or GbE Port Bit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHzX16 TDMTable of Contents 130 Table of Contents129 132List of Tables ClockingList of Tables 88F6281 Part Order Options 132 Hsbga 288-pin Package Dimensions 131Revision History 134 Pin and Signal Descriptions List of FiguresInter-IC Sound I2S Test Circuit 107 Related Documentation About this DocumentPreface Document Conventions Following conventions are used in this documentPin and Signal Descriptions Flash PowerPin Logic Misc PCI ExpressInterface Pin Prefix Codes Pin DescriptionsPin Functions and Assignments Table Key Term DefinitionMPP Twsi Uart 88F6281 Hardware Specifications Interface Pin Prefix CodesRTC SPI Sdio TDM PTPPower Pin Assignments Power Supply PinsPin Name Description Type 88F6281 Hardware Specifications Power Pin Assignments Miscellaneous Pin Assignment Pin Name Power Description Type RailMiscellaneous Pin Assignments Mclkout Sstl Vddm DDR Sdram Interface Pin AssignmentsDDR Sdram Interface Pin Assignments Mcke Sstl VddmBurstin Mpcal Mstartburst Sstl VddmMstart Sstl Vddm MncalPCI Express Interface Pin Assignments PCI Express Interface Pin AssignmentsSata Interface Pin Assignments Pin Name Power Rail Description TypeSata Port Interface Pin Assignment Gigabit Ethernet Port Interface Pin Assignments Pin Name Type Power Rail DescriptionGigabit Ethernet Port0/1 Interface Pin Assignments Gerxclk Cmos Vddgea Gerxctl Cmos VddgeaCmos Vddgeb MII/MMII Collision Detect Gmii Receive ErrorMPP2724 To any clockMII/MMII Receive Error MII/MMII Transmit ErrorGmii Transmit Error MPP32/GE112Gemdc Cmos Vddgea Serial Management Interface SMI Interface Pin AssignmentsSerial Management Interface SMI Pin Assignments Gemdio Cmos VddgeaUSB 2.0 Interface Pin Assignments USB 2.0 Interface Pin AssignmentsUSB 2.0 Data Differential Pair Jtag Interface Pin Assignment Jtag Pin AssignmentRtcxin Real Time Clock RTC Interface Pin AssignmentsRTC Interface Pin Assignments RtcxoutNfcle Cmos Vddo Nand Flash Interface Pin AssignmentNand Flash Interface Pin Assignment Nfale Cmos VddoMPP Interface Pin Assignment MPP Interface Pin AssignmentTwsda Cmos Vddo Two-Wire Serial Interface Twsi InterfaceTwo-Wire Serial Interface Twsi Interface Pin Assignment Twsck Cmos VddoUart Interface Uart Port 0/1 Interface Pin AssignmentMultiplexing option Audio S/PDIF / I2S Interface Signal AssignmentAudio S/PDIF / I2S Interface Fs is the audio sample rateSerial Peripheral Interface SPI Interface Serial Peripheral Interface SPI Interface Signal AssignmentPin Name Pin Type Power Rail Description SPICSnSdclk Cmos Vddo Secure Digital Input/Output Sdio InterfaceSdcmd Cmos Vddo Time Division Multiplexing TDM Interface Signal Assignment Time Division Multiplexing TDM InterfaceTdmspimosi Cmos Vddo Tdmspimiso Cmos VddoTransport Stream TS Interface Signal Assignment Transport Stream TS InterfaceTSMP9 Cmos Vddo TSMP7 Cmos VddoTSMP8 Cmos Vddo Cmos Vddo TS0DATA6 VddgebPtpclk Cmos Vddo Precise Timing Protocol PTP Interface Signal AssignmentPrecise Timing Protocol PTP Interface Ptpeventreq Cmos VddoInternal Pull-up and Pull-down Pins Internal Pull-up and Pull-down PinsPin Name Pin Number Pull up/Pull down Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 Pin Map and Pin List 88F6281 pin list is provided as an Excel file attachmentPin Multiplexing Multi-Purpose Pins Functional SummaryPin Multiplexing Gpio MPP FunctionalityMPP190 MPP3520 MPP4936 Sata LEDs Audio Nand flash GbEMPP Function Summary Sysrsto SpimosiMPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Gigabit Ethernet GbE Pins Multiplexing on MPP Ethernet Ports Pins MultiplexingMPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 Tsmp TS Multiplexing Pins on MPP TS Port Pin MultiplexingLists the clocks in the 88F6281 Clocking88F6281Clocks Clock Type DescriptionSata PHY PLL Clocking 88F6281ClocksSupported Clock Combinations Ptpclk88F6192, and 88F6281 Functional Specifications Spread Spectrum Clock Generator SscgPower-Up Sequence Requirements System Power Up/Down and Reset SettingsPower-Up/Down Sequence Requirements System Power Up/Down and Reset SettingsPower-Down Sequence Requirements Hardware Reset88F6281 May reset all settings to the factory default values Reset Out SignalPower On Reset POR SYSRSTn Duration CounterPins Sample Configuration PCI Express ResetSheeva CPU TAP Controller Reset PCI Express Root Complex ResetPin Configuration Function Reset ConfigurationThan the third Tclk cycle after SYSRSTn de-assertion 0x0-0x3 = Reserved MPP33 Cpuclk to DDR CLK Ratio0x4 = = Disable Sscg Disable= Enable PCI Express Clock 100 MHz Differential Clock ConfigurationSerial ROM Initialization 88F6281 Hardware Specifications Reset ConfigurationPin Configuration Function MPP18 Reserved Serial ROM Data StructureBoot Sequence Serial ROM Initialization Operation88F6281 Hardware Specifications Instruction Register Jtag InterfaceTAP Controller Jtag InterfaceID Register Bypass RegisterJtag Scan Chain Idcode Register MapAbsolute Maximum Ratings Electrical Specifications PreliminaryElectrical Specifications Preliminary Absolute Maximum Ratings125 Storage temperature 88F6281 Hardware Specifications Absolute Maximum Ratings125 Case temperature RTC interfaceParameter Min Typ Max Units Comments Recommended Operating ConditionsRecommended Operating Conditions MPP, TWSI, JTAG, SDIO, I 2S, SPI105 Junction Temperature Analog supply for RTC in BatteryBack-up mode Internal clock inverter for crystalThermal Power Dissipation Thermal Power DissipationCurrent Consumption Interface Symbol Test Conditions Max UnitsCurrent Consumption CPU @ 1000 MHzElectrical Specifications DC Electrical SpecificationsGeneral 3.3V Cmos DC Electrical Specifications General 3.3V Interface Cmos DC Electrical SpecificationsVIH Rgmii 1.8V Interface Cmos DC Electrical Specifications35*VDDIO Input high level 65*VDDIOSdram DDR2 Interface DC Electrical Specifications Sdram DDR2 Interface DC Electrical SpecificationsRTT Following table, Vddio means the Vddo power rail Twsi Interface 3.3V DC Electrical SpecificationsSPI Interface 3.3V DC Electrical Specifications Following table Vddio means the Vddo power railTDM Interface 3.3V DC Electrical Specifications Reference Clock AC Timing Specifications AC Electrical SpecificationsReference Clock AC Timing Specifications Twsi Master Mode Reference Clock Description Symbol Min Max Units Tdmspi Output ClockSMI Master Mode Reference Clock TclkSdram DDR2 Interface AC Timing Table MHz @ Description Symbol Min MaxSdram DDR2 Interface AC Timing Sdram DDR2 Interface AC Timing TableMHz @ Description Symbol Min Max Units Sdram DDR2 Interface Address Timing TableSdram DDR2 Clock Specifications Sdram DDR2 Clock SpecificationsDescription Symbol Min Max Units VTT Sdram DDR2 Interface AC Timing DiagramsSdram DDR2 Interface Test Circuit CLKControl AddressDQSn TDSI tDHI Rgmii 10/100/1000 AC Timing Table at Reduced Gigabit Media Independent Interface Rgmii AC TimingRgmii AC Timing Table Rgmii 10/100 AC Timing Table atRgmii AC Timing Diagram Rgmii Test CircuitGmii AC Timing Table 125 MHz Description Symbol Min MaxGigabit Media Independent Interface Gmii AC Timing Gmii Test CircuitVILmax Gmii AC Timing DiagramsTSETUP Hold TLOW THIGH5.3 MII/MMII MAC Mode AC Timing Diagrams 5.1 MII/MMII MAC Mode AC Timing Table5.2 MII/MMII MAC Mode Test Circuit MII/MMII MAC Mode AC Timing TableMII/MMII MAC Mode Input AC Timing Diagram SMI Master Mode AC Timing Table SMI Master Mode AC Timing TableSMI Master Mode Test Circuit Serial Management Interface SMI AC TimingSMI Master Mode AC Timing Diagrams MDCJtag Interface AC Timing Table 30 MHz Description Symbol Min Max UnitsJtag Interface AC Timing Jtag Interface Test CircuitJtag Interface AC Timing Diagrams Jtag Interface Output Delay AC Timing DiagramTwsi AC Timing Table Two-Wire Serial Interface Twsi AC Timing100 kHz Description Symbol Twsi Master AC Timing TableTwsi AC Timing Diagrams Twsi Test Circuit9.1 S/PDIF AC Timing Table Sony/Philips Digital Interconnect Format S/PDIF AC TimingPdif AC Timing Table 9.2 S/PDIF Test Circuit Pdif Test CircuitInter-IC Sound I2S Test Circuit Inter-IC Sound Interface I2S AC TimingInter-IC Sound I2S AC Timing Table Inter-IC Sound I2S AC Timing TableInter-IC Sound I2S AC Timing Diagrams Inter-IC Sound I2S Output Delay AC Timing DiagramTDM Interface AC Timing Table 192 MHz Description Symbol Min Max UnitsTime Division Multiplexing TDM Interface AC Timing TDM Interface Test CircuitPclk DTX TDM Interface Timing DiagramsPclk DRX SPI Master Mode AC Timing Table SPI Master Mode AC Timing TableSPI Master Mode Test Circuit Description Symbol Min MaxSclk SPI Master Mode Timing DiagramsTCH tCL Data Out TDOVmin TDOVmax TCSB TCSASecure Digital Input/Output Sdio AC Timing Table Sdio Host in High Speed Mode AC Timing TableSecure Digital Input/Output Sdio Interface AC Timing Secure Digital Input/Output Sdio Test CircuitSecure Digital Input/Output Sdio AC Timing Diagrams Sdio Host in High Speed Mode Output AC Timing DiagramTransport Stream Output Interface AC Timing Table Transport Stream TS Interface AC TimingTransport Stream Interface AC Timing Table Transport Stream Input Interface AC Timing TableTransport Stream Interface Timing Diagrams Transport Stream Interface Test CircuitTransport Stream Input Interface AC Timing Diagram Differential Interface Reference Clock Characteristics Differential Interface Electrical CharacteristicsClock frequency FCK 100.0 PCI Express Interface Spread Spectrum Requirements Symbol Min Max UnitsFmod 33.0 PCI Express Interface Driver and Receiver Characteristics PCI Express Interface Electrical CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test CircuitSata Interface Electrical Characteristics DJ5 RlodTJ5 Rlid275.0 750.0 Differential return loss 150 MHz-300 MHz Differential return loss 600 MHz-2.4 GHzDifferential return loss 3.0 GHz-5.0 GHz 18.0 Differential return loss 300 MHz-600 MHzUSB Low Speed Driver and Receiver Characteristics USB Electrical CharacteristicsUSB Driver and Receiver Characteristics Low Speed Description Sym bol Min Max UnitsFull Speed Description Min MaxHigh Speed Description Symbol Min Max USB High Speed Driver and Receiver CharacteristicsUSB Interface Driver Waveforms High Speed TX Eye Diagram Pattern Template Thermal Data Preliminary Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/sThermal Data Preliminary Hsbga 288-pin Package and Dimensions PackagePackage Package Hsbga 288-pin Package DimensionsSymbol Common Dimension Millimeters Hsbga88F6281 -xx-BIA2Cxxx-xxxx Part Order Numbering/Package MarkingPart Order Numbering 88F6281 Part Order OptionsPackage Marking Part Order Numbering/Package MarkingRevision History Revision Date Comments, Power Pin Assignments, on Revision HistoryRevised , Reference Clock AC Timing Specifications, on January 28 Initial release , Current Consumption, on page 80 added the followingThis page is Intentionally Left Blank Page Marvell. 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