88F6281

Hardware Specifications

8.6.12.3SPI (Master Mode) Timing Diagrams

Figure 35: SPI (Master Mode) Output AC Timing Diagram

tCH tCL

SCLK

Data

Out

tDOVmin

tDOVmax

CS

tCSB

tCSA

Figure 36: SPI (Master Mode) Input AC Timing Diagram

SCLK

Data in

tSU

tHD

Doc. No. MV-S104859-U0 Rev. E

 

Copyright © 2008 Marvell

Page 112

Document Classification: Proprietary Information

December 2, 2008, Preliminary

Page 112
Image 112
Marvel Group 88F6281 specifications SPI Master Mode Timing Diagrams, TCH tCL, Sclk, Data Out TDOVmin TDOVmax TCSB TCSA