Manuals / Marvel Group / Computer Equipment / Computer Hardware

Marvel Group 88F6281 specifications TSMP0 Tdmspi Auspdifi

Models: 88F6281

1 140

Download 140 pages 58.14 Kb

Page 55

Pin Multiplexing

Multi-Purpose Pins Functional Summary

Table 26: MPP Function Summary (Continued)

	Pin name	0x0	0x1	0x2	0x3	0x4	0x5	0xC	0xD

	MPP[36]	GPIO[36]	TSMP[0]	TDM_SPI_	-	AU_SPDIFI	-	-	-
	MPP[36]	(in/out)	(in/out)	CS1 (out)	-	(in)	-	-	-
		(in/out)	(in/out)	CS1 (out)		(in)

	MPP[37]	GPIO[37]	TSMP[1]	TDM_CH2_	-	AU_SPDIF	-	-	-
	MPP[37]	(in/out)	(in/out)	TX_QL (out)	-	O (out)	-	-	-
		(in/out)	(in/out)	TX_QL (out)		O (out)

	MPP[38]	GPIO[38]	TSMP[2]	TDM_CH2_		AU_SPDIF
		GPIO[38]	TSMP[2]	TDM_CH2_	-	RMCLK	-	-	-
		(in/out)	(in/out)	RX_QL (out)	-	RMCLK	-	-	-
		(in/out)	(in/out)	RX_QL (out)		(out)
						(out)
	MPP[39]	GPIO[39]	TSMP[3]	TDM_SPI_	-	AU_I2SBCL	-	-	-
	MPP[39]	(in/out)	(in/out)	CS0 (out)	-	K (out)	-	-	-
		(in/out)	(in/out)	CS0 (out)		K (out)

	MPP[40]	GPIO[40]	TSMP[4]	TDM_SPI_	-	AU_I2SDO	-	-	-
	MPP[40]	(in/out)	(in/out)	SCK (out)	-	(out)	-	-	-
		(in/out)	(in/out)	SCK (out)		(out)

	MPP[41]	GPIO[41]	TSMP[5]	TDM_SPI_	-	AU_I2SLRC	-	-	-
	MPP[41]	(in/out)	(in/out)	MISO (in)	-	LK (out)	-	-	-
		(in/out)	(in/out)	MISO (in)		LK (out)

	MPP[42]	GPIO[42]	TSMP[6]	TDM_SPI_	-	AU_I2SMC	-	-	-
	MPP[42]	(in/out)	(in/out)	MOSI (out)	-	LK (out)	-	-	-
		(in/out)	(in/out)	MOSI (out)		LK (out)

	MPP[43]	GPIO[43]	TSMP[7]	TDM_COD		AU_I2SDI
		GPIO[43]	TSMP[7]	EC_INTn	-	AU_I2SDI	-	-	-
		(in/out)	(in/out)	EC_INTn	-	(in)	-	-	-
		(in/out)	(in/out)	(in)		(in)
				(in)
	MPP[44]	GPIO[44]	TSMP[8]	TDM_COD		AU_EXTCL
		GPIO[44]	TSMP[8]	EC_RSTn	-	AU_EXTCL	-	-	-
		(in/out)	(in/out)	EC_RSTn	-	K (in)	-	-	-
		(in/out)	(in/out)	(out)		K (in)
				(out)
	MPP[45]	GPIO[45]	TSMP[9]	TDM_PCLK	-	-	-	-	-
	MPP[45]	(in/out)	(in/out)	(in/out)	-	-	-	-	-
		(in/out)	(in/out)	(in/out)

	MPP[46]	GPIO[46]	TSMP[10]	TDM_FS	-	-	-	-	-
	MPP[46]	(in/out)	(in/out)	(in/out)	-	-	-	-	-
		(in/out)	(in/out)	(in/out)

	MPP[47]	GPIO[47]	TSMP[11]	TDM_DRX	-	-	-	-	-
	MPP[47]	(in/out)	(in/out)	(in)	-	-	-	-	-
		(in/out)	(in/out)	(in)

	MPP[48]	GPIO[48]	TSMP[12]	TDM_DTX	-	-	-	-	-
	MPP[48]	(in/out)	(in/out)	(out)	-	-	-	-	-
		(in/out)	(in/out)	(out)

	MPP[49]	GPIO[49]	-	TDM_CH0_	-	-	PTP_CLK	-	-
	MPP[49]	(in/out)	-	RX_QL (out)	-	-	(in)	-	-
		(in/out)		RX_QL (out)			(in)

Copyright © 2008 Marvell		Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary	Document Classification: Proprietary Information	Page 55

Image 55

Marvel Group 88F6281 specifications TSMP0 Tdmspi Auspdifi

Contents

88F6281 Hardware SpecificationsDocument Conventions Document Status 88F6281 Hardware SpecificationsDoc Status Preliminary Technical Publication 88F6281 Hardware SpecificationsIntegrated Controller High-performance CPU core, running at up to FeaturesSupports Ieee 802.1Qav draft Audio Video Bridging networks FeaturesBit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHz GbE Port 0 in Gmii mode or GbE PortTDM X16Table of Contents 132 Table of Contents129 130Clocking List of TablesList of Tables 88F6281 Part Order Options 132 Hsbga 288-pin Package Dimensions 131Revision History 134 List of Figures Pin and Signal DescriptionsInter-IC Sound I2S Test Circuit 107 Related Documentation About this DocumentPreface Following conventions are used in this document Document ConventionsPin and Signal Descriptions Misc PCI Express PowerPin Logic FlashTerm Definition Pin DescriptionsPin Functions and Assignments Table Key Interface Pin Prefix CodesSPI Sdio TDM PTP 88F6281 Hardware Specifications Interface Pin Prefix CodesRTC MPP Twsi UartPower Pin Assignments Power Supply PinsPin Name Description Type 88F6281 Hardware Specifications Power Pin Assignments Miscellaneous Pin Assignment Pin Name Power Description Type RailMiscellaneous Pin Assignments Mcke Sstl Vddm DDR Sdram Interface Pin AssignmentsDDR Sdram Interface Pin Assignments Mclkout Sstl VddmMncal Mstartburst Sstl VddmMstart Sstl Vddm Burstin MpcalPCI Express Interface Pin Assignments PCI Express Interface Pin AssignmentsSata Interface Pin Assignments Pin Name Power Rail Description TypeSata Port Interface Pin Assignment Gigabit Ethernet Port Interface Pin Assignments Pin Name Type Power Rail DescriptionGigabit Ethernet Port0/1 Interface Pin Assignments Gerxclk Cmos Vddgea Gerxctl Cmos VddgeaCmos Vddgeb To any clock Gmii Receive ErrorMPP2724 MII/MMII Collision DetectMPP32/GE112 MII/MMII Transmit ErrorGmii Transmit Error MII/MMII Receive ErrorGemdio Cmos Vddgea Serial Management Interface SMI Interface Pin AssignmentsSerial Management Interface SMI Pin Assignments Gemdc Cmos VddgeaUSB 2.0 Interface Pin Assignments USB 2.0 Interface Pin AssignmentsUSB 2.0 Data Differential Pair Jtag Pin Assignment Jtag Interface Pin AssignmentRtcxout Real Time Clock RTC Interface Pin AssignmentsRTC Interface Pin Assignments RtcxinNfale Cmos Vddo Nand Flash Interface Pin AssignmentNand Flash Interface Pin Assignment Nfcle Cmos VddoMPP Interface Pin Assignment MPP Interface Pin AssignmentTwsck Cmos Vddo Two-Wire Serial Interface Twsi InterfaceTwo-Wire Serial Interface Twsi Interface Pin Assignment Twsda Cmos VddoUart Port 0/1 Interface Pin Assignment Uart InterfaceFs is the audio sample rate Audio S/PDIF / I2S Interface Signal AssignmentAudio S/PDIF / I2S Interface Multiplexing optionSPICSn Serial Peripheral Interface SPI Interface Signal AssignmentPin Name Pin Type Power Rail Description Serial Peripheral Interface SPI InterfaceSdclk Cmos Vddo Secure Digital Input/Output Sdio InterfaceSdcmd Cmos Vddo Time Division Multiplexing TDM Interface Time Division Multiplexing TDM Interface Signal AssignmentTdmspimiso Cmos Vddo Tdmspimosi Cmos VddoTransport Stream TS Interface Transport Stream TS Interface Signal AssignmentCmos Vddo TS0DATA6 Vddgeb TSMP7 Cmos VddoTSMP8 Cmos Vddo TSMP9 Cmos VddoPtpeventreq Cmos Vddo Precise Timing Protocol PTP Interface Signal AssignmentPrecise Timing Protocol PTP Interface Ptpclk Cmos VddoInternal Pull-up and Pull-down Pins Internal Pull-up and Pull-down PinsPin Name Pin Number Pull up/Pull down Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 pin list is provided as an Excel file attachment 88F6281 Pin Map and Pin ListPin Multiplexing Multi-Purpose Pins Functional SummaryPin Multiplexing Sata LEDs Audio Nand flash GbE MPP FunctionalityMPP190 MPP3520 MPP4936 GpioSysrsto Spimosi MPP Function SummaryMPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Ethernet Ports Pins Multiplexing Gigabit Ethernet GbE Pins Multiplexing on MPPMPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 TS Port Pin Multiplexing Tsmp TS Multiplexing Pins on MPPClock Type Description Clocking88F6281Clocks Lists the clocks in the 88F6281Ptpclk Clocking 88F6281ClocksSupported Clock Combinations Sata PHY PLLSpread Spectrum Clock Generator Sscg 88F6192, and 88F6281 Functional SpecificationsSystem Power Up/Down and Reset Settings System Power Up/Down and Reset SettingsPower-Up/Down Sequence Requirements Power-Up Sequence RequirementsPower-Down Sequence Requirements Hardware Reset88F6281 SYSRSTn Duration Counter Reset Out SignalPower On Reset POR May reset all settings to the factory default valuesPCI Express Root Complex Reset PCI Express ResetSheeva CPU TAP Controller Reset Pins Sample ConfigurationPin Configuration Function Reset ConfigurationThan the third Tclk cycle after SYSRSTn de-assertion 0x0-0x3 = Reserved MPP33 Cpuclk to DDR CLK Ratio0x4 = PCI Express Clock 100 MHz Differential Clock Configuration Sscg Disable= Enable = DisableSerial ROM Data Structure 88F6281 Hardware Specifications Reset ConfigurationPin Configuration Function MPP18 Reserved Serial ROM InitializationSerial ROM Initialization Operation Boot Sequence88F6281 Hardware Specifications Jtag Interface Jtag InterfaceTAP Controller Instruction RegisterIdcode Register Map Bypass RegisterJtag Scan Chain ID RegisterAbsolute Maximum Ratings Electrical Specifications PreliminaryElectrical Specifications Preliminary Absolute Maximum RatingsRTC interface 88F6281 Hardware Specifications Absolute Maximum Ratings125 Case temperature 125 Storage temperatureMPP, TWSI, JTAG, SDIO, I 2S, SPI Recommended Operating ConditionsRecommended Operating Conditions Parameter Min Typ Max Units CommentsInternal clock inverter for crystal Analog supply for RTC in BatteryBack-up mode 105 Junction TemperatureThermal Power Dissipation Thermal Power DissipationCPU @ 1000 MHz Interface Symbol Test Conditions Max UnitsCurrent Consumption Current ConsumptionGeneral 3.3V Interface Cmos DC Electrical Specifications DC Electrical SpecificationsGeneral 3.3V Cmos DC Electrical Specifications Electrical Specifications65*VDDIO Rgmii 1.8V Interface Cmos DC Electrical Specifications35*VDDIO Input high level VIHSdram DDR2 Interface DC Electrical Specifications Sdram DDR2 Interface DC Electrical SpecificationsRTT Following table Vddio means the Vddo power rail Twsi Interface 3.3V DC Electrical SpecificationsSPI Interface 3.3V DC Electrical Specifications Following table, Vddio means the Vddo power railTDM Interface 3.3V DC Electrical Specifications Reference Clock AC Timing Specifications AC Electrical SpecificationsReference Clock AC Timing Specifications Tclk Description Symbol Min Max Units Tdmspi Output ClockSMI Master Mode Reference Clock Twsi Master Mode Reference ClockSdram DDR2 Interface AC Timing Table MHz @ Description Symbol Min MaxSdram DDR2 Interface AC Timing Sdram DDR2 Interface AC Timing TableSdram DDR2 Interface Address Timing Table MHz @ Description Symbol Min Max UnitsSdram DDR2 Clock Specifications Sdram DDR2 Clock SpecificationsDescription Symbol Min Max Units CLK Sdram DDR2 Interface AC Timing DiagramsSdram DDR2 Interface Test Circuit VTTControl AddressDQSn TDSI tDHI Rgmii 10/100 AC Timing Table at Reduced Gigabit Media Independent Interface Rgmii AC TimingRgmii AC Timing Table Rgmii 10/100/1000 AC Timing Table atRgmii Test Circuit Rgmii AC Timing DiagramGmii Test Circuit 125 MHz Description Symbol Min MaxGigabit Media Independent Interface Gmii AC Timing Gmii AC Timing TableTLOW THIGH Gmii AC Timing DiagramsTSETUP Hold VILmaxMII/MMII MAC Mode AC Timing Table 5.1 MII/MMII MAC Mode AC Timing Table5.2 MII/MMII MAC Mode Test Circuit 5.3 MII/MMII MAC Mode AC Timing DiagramsMII/MMII MAC Mode Input AC Timing Diagram Serial Management Interface SMI AC Timing SMI Master Mode AC Timing TableSMI Master Mode Test Circuit SMI Master Mode AC Timing TableMDC SMI Master Mode AC Timing DiagramsJtag Interface Test Circuit 30 MHz Description Symbol Min Max UnitsJtag Interface AC Timing Jtag Interface AC Timing TableJtag Interface Output Delay AC Timing Diagram Jtag Interface AC Timing DiagramsTwsi Master AC Timing Table Two-Wire Serial Interface Twsi AC Timing100 kHz Description Symbol Twsi AC Timing TableTwsi Test Circuit Twsi AC Timing Diagrams9.1 S/PDIF AC Timing Table Sony/Philips Digital Interconnect Format S/PDIF AC TimingPdif AC Timing Table Pdif Test Circuit 9.2 S/PDIF Test CircuitInter-IC Sound I2S AC Timing Table Inter-IC Sound Interface I2S AC TimingInter-IC Sound I2S AC Timing Table Inter-IC Sound I2S Test CircuitInter-IC Sound I2S Output Delay AC Timing Diagram Inter-IC Sound I2S AC Timing DiagramsTDM Interface Test Circuit 192 MHz Description Symbol Min Max UnitsTime Division Multiplexing TDM Interface AC Timing TDM Interface AC Timing TablePclk DTX TDM Interface Timing DiagramsPclk DRX Description Symbol Min Max SPI Master Mode AC Timing TableSPI Master Mode Test Circuit SPI Master Mode AC Timing TableData Out TDOVmin TDOVmax TCSB TCSA SPI Master Mode Timing DiagramsTCH tCL SclkSecure Digital Input/Output Sdio Test Circuit Sdio Host in High Speed Mode AC Timing TableSecure Digital Input/Output Sdio Interface AC Timing Secure Digital Input/Output Sdio AC Timing TableSdio Host in High Speed Mode Output AC Timing Diagram Secure Digital Input/Output Sdio AC Timing DiagramsTransport Stream Input Interface AC Timing Table Transport Stream TS Interface AC TimingTransport Stream Interface AC Timing Table Transport Stream Output Interface AC Timing TableTransport Stream Interface Test Circuit Transport Stream Interface Timing DiagramsTransport Stream Input Interface AC Timing Diagram Differential Interface Reference Clock Characteristics Differential Interface Electrical CharacteristicsClock frequency FCK 100.0 PCI Express Interface Spread Spectrum Requirements Symbol Min Max UnitsFmod 33.0 PCI Express Interface Driver and Receiver Characteristics PCI Express Interface Electrical CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test CircuitSata Interface Electrical Characteristics Rlid RlodTJ5 DJ518.0 Differential return loss 300 MHz-600 MHz Differential return loss 600 MHz-2.4 GHzDifferential return loss 3.0 GHz-5.0 GHz 275.0 750.0 Differential return loss 150 MHz-300 MHzLow Speed Description Sym bol Min Max Units USB Electrical CharacteristicsUSB Driver and Receiver Characteristics USB Low Speed Driver and Receiver CharacteristicsMin Max Full Speed DescriptionHigh Speed Description Symbol Min Max USB High Speed Driver and Receiver CharacteristicsUSB Interface Driver Waveforms High Speed TX Eye Diagram Pattern Template Thermal Data Preliminary Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/sThermal Data Preliminary Package Hsbga 288-pin Package and DimensionsHsbga Package Hsbga 288-pin Package DimensionsSymbol Common Dimension Millimeters Package88F6281 Part Order Options Part Order Numbering/Package MarkingPart Order Numbering 88F6281 -xx-BIA2Cxxx-xxxxPart Order Numbering/Package Marking Package MarkingRevision Date Comments Revision HistoryRevision History , Power Pin Assignments, onRevised , Reference Clock AC Timing Specifications, on , Current Consumption, on page 80 added the following January 28 Initial releaseThis page is Intentionally Left Blank Page Marvell. Moving Forward Faster