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Marvel Group 88F6281 specifications High Speed TX Eye Diagram Pattern Template

Models: 88F6281

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88F6281

Hardware Specifications

Figure 45: High Speed TX Eye Diagram Pattern Template

+525mV
+475mV
			+400mV
			Differential
+300mV
			0 Volts
			Differential
-300mV
			- 400mV
			Differential
-475mV
-525mV
7.5%	37.5%	62.5%	92.5%
0%			100%

Figure 46: High Speed RX Eye Diagram Pattern Template

+525mV

+475mV

+400mV

Differential

+175mV

0 Volts

Differential

-175mV

- 400mV

Differential

-475mV -525mV

12.5%	35	65	87.5%
0%			100%

Doc. No. MV-S104859-U0 Rev. E		Copyright © 2008 Marvell
Page 128	Document Classification: Proprietary Information	December 2, 2008, Preliminary

Page 128

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Marvel Group 88F6281 specifications High Speed TX Eye Diagram Pattern Template

Contents

Hardware Specifications 88F6281Doc Status Preliminary Technical Publication 88F6281 Hardware SpecificationsDocument Conventions Document Status Integrated Controller Hardware Specifications88F6281 Features High-performance CPU core, running at up toFeatures Supports Ieee 802.1Qav draft Audio Video Bridging networksGbE Port 0 in Gmii mode or GbE Port Bit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHzX16 TDMTable of Contents Table of Contents 129130 132List of Tables ClockingList of Tables Revision History 134 Hsbga 288-pin Package Dimensions 13188F6281 Part Order Options 132 Pin and Signal Descriptions List of FiguresInter-IC Sound I2S Test Circuit 107 Preface About this DocumentRelated Documentation Document Conventions Following conventions are used in this documentPin and Signal Descriptions Power Pin LogicFlash Misc PCI ExpressPin Descriptions Pin Functions and Assignments Table KeyInterface Pin Prefix Codes Term Definition88F6281 Hardware Specifications Interface Pin Prefix Codes RTCMPP Twsi Uart SPI Sdio TDM PTPPin Name Description Type Power Supply PinsPower Pin Assignments 88F6281 Hardware Specifications Power Pin Assignments Miscellaneous Pin Assignments Pin Name Power Description Type RailMiscellaneous Pin Assignment DDR Sdram Interface Pin Assignments DDR Sdram Interface Pin AssignmentsMclkout Sstl Vddm Mcke Sstl VddmMstartburst Sstl Vddm Mstart Sstl VddmBurstin Mpcal MncalPCI Express Interface Pin Assignments PCI Express Interface Pin AssignmentsSata Port Interface Pin Assignment Pin Name Power Rail Description TypeSata Interface Pin Assignments Gigabit Ethernet Port0/1 Interface Pin Assignments Pin Name Type Power Rail DescriptionGigabit Ethernet Port Interface Pin Assignments Cmos Vddgeb Gerxctl Cmos VddgeaGerxclk Cmos Vddgea Gmii Receive Error MPP2724MII/MMII Collision Detect To any clockMII/MMII Transmit Error Gmii Transmit ErrorMII/MMII Receive Error MPP32/GE112Serial Management Interface SMI Interface Pin Assignments Serial Management Interface SMI Pin AssignmentsGemdc Cmos Vddgea Gemdio Cmos VddgeaUSB 2.0 Data Differential Pair USB 2.0 Interface Pin AssignmentsUSB 2.0 Interface Pin Assignments Jtag Interface Pin Assignment Jtag Pin AssignmentReal Time Clock RTC Interface Pin Assignments RTC Interface Pin AssignmentsRtcxin RtcxoutNand Flash Interface Pin Assignment Nand Flash Interface Pin AssignmentNfcle Cmos Vddo Nfale Cmos VddoMPP Interface Pin Assignment MPP Interface Pin AssignmentTwo-Wire Serial Interface Twsi Interface Two-Wire Serial Interface Twsi Interface Pin AssignmentTwsda Cmos Vddo Twsck Cmos VddoUart Interface Uart Port 0/1 Interface Pin AssignmentAudio S/PDIF / I2S Interface Signal Assignment Audio S/PDIF / I2S InterfaceMultiplexing option Fs is the audio sample rateSerial Peripheral Interface SPI Interface Signal Assignment Pin Name Pin Type Power Rail DescriptionSerial Peripheral Interface SPI Interface SPICSnSdcmd Cmos Vddo Secure Digital Input/Output Sdio InterfaceSdclk Cmos Vddo Time Division Multiplexing TDM Interface Signal Assignment Time Division Multiplexing TDM InterfaceTdmspimosi Cmos Vddo Tdmspimiso Cmos VddoTransport Stream TS Interface Signal Assignment Transport Stream TS InterfaceTSMP7 Cmos Vddo TSMP8 Cmos VddoTSMP9 Cmos Vddo Cmos Vddo TS0DATA6 VddgebPrecise Timing Protocol PTP Interface Signal Assignment Precise Timing Protocol PTP InterfacePtpclk Cmos Vddo Ptpeventreq Cmos VddoPin Name Pin Number Pull up/Pull down Internal Pull-up and Pull-down PinsInternal Pull-up and Pull-down Pins Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 Pin Map and Pin List 88F6281 pin list is provided as an Excel file attachmentPin Multiplexing Multi-Purpose Pins Functional SummaryPin Multiplexing MPP Functionality MPP190 MPP3520 MPP4936Gpio Sata LEDs Audio Nand flash GbEMPP Function Summary Sysrsto SpimosiMPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Gigabit Ethernet GbE Pins Multiplexing on MPP Ethernet Ports Pins MultiplexingMPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 Tsmp TS Multiplexing Pins on MPP TS Port Pin MultiplexingClocking 88F6281ClocksLists the clocks in the 88F6281 Clock Type DescriptionClocking 88F6281Clocks Supported Clock CombinationsSata PHY PLL Ptpclk88F6192, and 88F6281 Functional Specifications Spread Spectrum Clock Generator SscgSystem Power Up/Down and Reset Settings Power-Up/Down Sequence RequirementsPower-Up Sequence Requirements System Power Up/Down and Reset Settings88F6281 Hardware ResetPower-Down Sequence Requirements Reset Out Signal Power On Reset PORMay reset all settings to the factory default values SYSRSTn Duration CounterPCI Express Reset Sheeva CPU TAP Controller ResetPins Sample Configuration PCI Express Root Complex ResetThan the third Tclk cycle after SYSRSTn de-assertion Reset ConfigurationPin Configuration Function 0x4 = MPP33 Cpuclk to DDR CLK Ratio0x0-0x3 = Reserved Sscg Disable = Enable= Disable PCI Express Clock 100 MHz Differential Clock Configuration88F6281 Hardware Specifications Reset Configuration Pin Configuration Function MPP18 ReservedSerial ROM Initialization Serial ROM Data StructureBoot Sequence Serial ROM Initialization Operation88F6281 Hardware Specifications Jtag Interface TAP ControllerInstruction Register Jtag InterfaceBypass Register Jtag Scan ChainID Register Idcode Register MapElectrical Specifications Preliminary Electrical Specifications PreliminaryAbsolute Maximum Ratings Absolute Maximum Ratings88F6281 Hardware Specifications Absolute Maximum Ratings 125 Case temperature125 Storage temperature RTC interfaceRecommended Operating Conditions Recommended Operating ConditionsParameter Min Typ Max Units Comments MPP, TWSI, JTAG, SDIO, I 2S, SPIAnalog supply for RTC in Battery Back-up mode105 Junction Temperature Internal clock inverter for crystalThermal Power Dissipation Thermal Power DissipationInterface Symbol Test Conditions Max Units Current ConsumptionCurrent Consumption CPU @ 1000 MHzDC Electrical Specifications General 3.3V Cmos DC Electrical SpecificationsElectrical Specifications General 3.3V Interface Cmos DC Electrical SpecificationsRgmii 1.8V Interface Cmos DC Electrical Specifications 35*VDDIO Input high levelVIH 65*VDDIORTT Sdram DDR2 Interface DC Electrical SpecificationsSdram DDR2 Interface DC Electrical Specifications Twsi Interface 3.3V DC Electrical Specifications SPI Interface 3.3V DC Electrical SpecificationsFollowing table, Vddio means the Vddo power rail Following table Vddio means the Vddo power railTDM Interface 3.3V DC Electrical Specifications Reference Clock AC Timing Specifications AC Electrical SpecificationsReference Clock AC Timing Specifications Description Symbol Min Max Units Tdmspi Output Clock SMI Master Mode Reference ClockTwsi Master Mode Reference Clock TclkMHz @ Description Symbol Min Max Sdram DDR2 Interface AC TimingSdram DDR2 Interface AC Timing Table Sdram DDR2 Interface AC Timing TableMHz @ Description Symbol Min Max Units Sdram DDR2 Interface Address Timing TableDescription Symbol Min Max Units Sdram DDR2 Clock SpecificationsSdram DDR2 Clock Specifications Sdram DDR2 Interface AC Timing Diagrams Sdram DDR2 Interface Test CircuitVTT CLKDQSn TDSI tDHI AddressControl Reduced Gigabit Media Independent Interface Rgmii AC Timing Rgmii AC Timing TableRgmii 10/100/1000 AC Timing Table at Rgmii 10/100 AC Timing Table atRgmii AC Timing Diagram Rgmii Test Circuit125 MHz Description Symbol Min Max Gigabit Media Independent Interface Gmii AC TimingGmii AC Timing Table Gmii Test CircuitGmii AC Timing Diagrams TSETUP HoldVILmax TLOW THIGH5.1 MII/MMII MAC Mode AC Timing Table 5.2 MII/MMII MAC Mode Test Circuit5.3 MII/MMII MAC Mode AC Timing Diagrams MII/MMII MAC Mode AC Timing TableMII/MMII MAC Mode Input AC Timing Diagram SMI Master Mode AC Timing Table SMI Master Mode Test CircuitSMI Master Mode AC Timing Table Serial Management Interface SMI AC TimingSMI Master Mode AC Timing Diagrams MDC30 MHz Description Symbol Min Max Units Jtag Interface AC TimingJtag Interface AC Timing Table Jtag Interface Test CircuitJtag Interface AC Timing Diagrams Jtag Interface Output Delay AC Timing DiagramTwo-Wire Serial Interface Twsi AC Timing 100 kHz Description SymbolTwsi AC Timing Table Twsi Master AC Timing TableTwsi AC Timing Diagrams Twsi Test CircuitPdif AC Timing Table Sony/Philips Digital Interconnect Format S/PDIF AC Timing9.1 S/PDIF AC Timing Table 9.2 S/PDIF Test Circuit Pdif Test CircuitInter-IC Sound Interface I2S AC Timing Inter-IC Sound I2S AC Timing TableInter-IC Sound I2S Test Circuit Inter-IC Sound I2S AC Timing TableInter-IC Sound I2S AC Timing Diagrams Inter-IC Sound I2S Output Delay AC Timing Diagram192 MHz Description Symbol Min Max Units Time Division Multiplexing TDM Interface AC TimingTDM Interface AC Timing Table TDM Interface Test CircuitPclk DRX TDM Interface Timing DiagramsPclk DTX SPI Master Mode AC Timing Table SPI Master Mode Test CircuitSPI Master Mode AC Timing Table Description Symbol Min MaxSPI Master Mode Timing Diagrams TCH tCLSclk Data Out TDOVmin TDOVmax TCSB TCSASdio Host in High Speed Mode AC Timing Table Secure Digital Input/Output Sdio Interface AC TimingSecure Digital Input/Output Sdio AC Timing Table Secure Digital Input/Output Sdio Test CircuitSecure Digital Input/Output Sdio AC Timing Diagrams Sdio Host in High Speed Mode Output AC Timing DiagramTransport Stream TS Interface AC Timing Transport Stream Interface AC Timing TableTransport Stream Output Interface AC Timing Table Transport Stream Input Interface AC Timing TableTransport Stream Interface Timing Diagrams Transport Stream Interface Test CircuitTransport Stream Input Interface AC Timing Diagram Clock frequency FCK 100.0 Differential Interface Electrical CharacteristicsDifferential Interface Reference Clock Characteristics Fmod 33.0 Symbol Min Max UnitsPCI Express Interface Spread Spectrum Requirements PCI Express Interface Driver and Receiver Characteristics PCI Express Interface Electrical CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test CircuitSata Interface Electrical Characteristics Rlod TJ5DJ5 RlidDifferential return loss 600 MHz-2.4 GHz Differential return loss 3.0 GHz-5.0 GHz275.0 750.0 Differential return loss 150 MHz-300 MHz 18.0 Differential return loss 300 MHz-600 MHzUSB Electrical Characteristics USB Driver and Receiver CharacteristicsUSB Low Speed Driver and Receiver Characteristics Low Speed Description Sym bol Min Max UnitsFull Speed Description Min MaxUSB Interface Driver Waveforms USB High Speed Driver and Receiver CharacteristicsHigh Speed Description Symbol Min Max High Speed TX Eye Diagram Pattern Template Thermal Data Preliminary Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/sThermal Data Preliminary Hsbga 288-pin Package and Dimensions PackagePackage Hsbga 288-pin Package Dimensions Symbol Common Dimension MillimetersPackage HsbgaPart Order Numbering/Package Marking Part Order Numbering88F6281 -xx-BIA2Cxxx-xxxx 88F6281 Part Order OptionsPackage Marking Part Order Numbering/Package MarkingRevision History Revision Date Comments, Power Pin Assignments, on Revision HistoryRevised , Reference Clock AC Timing Specifications, on January 28 Initial release , Current Consumption, on page 80 added the followingThis page is Intentionally Left Blank Page Marvell. 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