Unused Interface Strapping | Marvel Group 88F6281 guide

Unused Interface Strapping

2 Unused Interface Strapping

Table 24 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not connected).

Table 24: Unused Interface Strapping

Unused Interface	Strapping

Ethernet SMI	Pull up GE_MDIO.

MPP	Configure any unused MPP pin to GPIO output.
	Leave the power supply connected.
	• If the related power supply is VDDO, leave it connected to 3.3V.
	• If the related power supply is VDD_GE_B, leave it connected to either 3.3V or 1.8V.

USB	Discard the power filter.
	Leave USB_AVDD connected to 3.3V.
	All other signals can be left unconnected.

PCI Express	Discard the analog power filters.
	Leave PEX_AVDD connected to 1.8V.
	Pull down the PEX_CLK_N signal through a 50 kΩ resistor to GND.
	Pull up the PEX_CLK_P signal through a 16 kΩ resistor to 1.8V.
	All other signals can be left unconnected.
	Configure the PEX_CLK_P and PEX_CLK_N signals as inputs, as indicated in Table 32,
	Reset Configuration, on page 67.

SATA	Discard the analog power filters.
	SATA0_AVDD/SATA1_AVDD can be left unconnected.

RTC	Connect RTC_AVDD, RTC_AVSS, RTC_XIN, and RTC_XOUT to GND.

SSCG	Discard the power filter.
	Leave SSCG_AVDD connected to 1.8V.

eFuse	Connect VHV to VDD

Copyright © 2008 Marvell		Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary	Document Classification: Proprietary Information	Page 49

Image 49

Marvel Group 88F6281 specifications Unused Interface Strapping

Contents

88F6281 Hardware Specifications Document Conventions Document Status 88F6281 Hardware SpecificationsDoc Status Preliminary Technical Publication 88F6281 Hardware SpecificationsIntegrated Controller High-performance CPU core, running at up to Features Supports Ieee 802.1Qav draft Audio Video Bridging networks Features Bit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHz GbE Port 0 in Gmii mode or GbE Port TDM X16 Table of Contents 129 Table of Contents130 132 Clocking List of Tables List of Tables 88F6281 Part Order Options 132 Hsbga 288-pin Package Dimensions 131Revision History 134 List of Figures Pin and Signal Descriptions Inter-IC Sound I2S Test Circuit 107 Related Documentation About this DocumentPreface Following conventions are used in this document Document Conventions Pin and Signal Descriptions Pin Logic PowerFlash Misc PCI Express Pin Functions and Assignments Table Key Pin DescriptionsInterface Pin Prefix Codes Term Definition RTC 88F6281 Hardware Specifications Interface Pin Prefix CodesMPP Twsi Uart SPI Sdio TDM PTP Power Pin Assignments Power Supply PinsPin Name Description Type 88F6281 Hardware Specifications Power Pin Assignments Miscellaneous Pin Assignment Pin Name Power Description Type RailMiscellaneous Pin Assignments DDR Sdram Interface Pin Assignments DDR Sdram Interface Pin AssignmentsMclkout Sstl Vddm Mcke Sstl Vddm Mstart Sstl Vddm Mstartburst Sstl VddmBurstin Mpcal Mncal PCI Express Interface Pin Assignments PCI Express Interface Pin Assignments Sata Interface Pin Assignments Pin Name Power Rail Description TypeSata Port Interface Pin Assignment Gigabit Ethernet Port Interface Pin Assignments Pin Name Type Power Rail DescriptionGigabit Ethernet Port0/1 Interface Pin Assignments Gerxclk Cmos Vddgea Gerxctl Cmos VddgeaCmos Vddgeb MPP2724 Gmii Receive ErrorMII/MMII Collision Detect To any clock Gmii Transmit Error MII/MMII Transmit ErrorMII/MMII Receive Error MPP32/GE112 Serial Management Interface SMI Pin Assignments Serial Management Interface SMI Interface Pin AssignmentsGemdc Cmos Vddgea Gemdio Cmos Vddgea USB 2.0 Interface Pin Assignments USB 2.0 Interface Pin AssignmentsUSB 2.0 Data Differential Pair Jtag Pin Assignment Jtag Interface Pin Assignment RTC Interface Pin Assignments Real Time Clock RTC Interface Pin AssignmentsRtcxin Rtcxout Nand Flash Interface Pin Assignment Nand Flash Interface Pin AssignmentNfcle Cmos Vddo Nfale Cmos Vddo MPP Interface Pin Assignment MPP Interface Pin Assignment Two-Wire Serial Interface Twsi Interface Pin Assignment Two-Wire Serial Interface Twsi InterfaceTwsda Cmos Vddo Twsck Cmos Vddo Uart Port 0/1 Interface Pin Assignment Uart Interface Audio S/PDIF / I2S Interface Audio S/PDIF / I2S Interface Signal AssignmentMultiplexing option Fs is the audio sample rate Pin Name Pin Type Power Rail Description Serial Peripheral Interface SPI Interface Signal AssignmentSerial Peripheral Interface SPI Interface SPICSn Sdclk Cmos Vddo Secure Digital Input/Output Sdio InterfaceSdcmd Cmos Vddo Time Division Multiplexing TDM Interface Time Division Multiplexing TDM Interface Signal Assignment Tdmspimiso Cmos Vddo Tdmspimosi Cmos Vddo Transport Stream TS Interface Transport Stream TS Interface Signal Assignment TSMP8 Cmos Vddo TSMP7 Cmos VddoTSMP9 Cmos Vddo Cmos Vddo TS0DATA6 Vddgeb Precise Timing Protocol PTP Interface Precise Timing Protocol PTP Interface Signal AssignmentPtpclk Cmos Vddo Ptpeventreq Cmos Vddo Internal Pull-up and Pull-down Pins Internal Pull-up and Pull-down PinsPin Name Pin Number Pull up/Pull down Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 pin list is provided as an Excel file attachment 88F6281 Pin Map and Pin List Pin Multiplexing Multi-Purpose Pins Functional SummaryPin Multiplexing MPP190 MPP3520 MPP4936 MPP FunctionalityGpio Sata LEDs Audio Nand flash GbE Sysrsto Spimosi MPP Function Summary MPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Ethernet Ports Pins Multiplexing Gigabit Ethernet GbE Pins Multiplexing on MPP MPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 TS Port Pin Multiplexing Tsmp TS Multiplexing Pins on MPP 88F6281Clocks ClockingLists the clocks in the 88F6281 Clock Type Description Supported Clock Combinations Clocking 88F6281ClocksSata PHY PLL Ptpclk Spread Spectrum Clock Generator Sscg 88F6192, and 88F6281 Functional Specifications Power-Up/Down Sequence Requirements System Power Up/Down and Reset SettingsPower-Up Sequence Requirements System Power Up/Down and Reset Settings Power-Down Sequence Requirements Hardware Reset88F6281 Power On Reset POR Reset Out SignalMay reset all settings to the factory default values SYSRSTn Duration Counter Sheeva CPU TAP Controller Reset PCI Express ResetPins Sample Configuration PCI Express Root Complex Reset Pin Configuration Function Reset ConfigurationThan the third Tclk cycle after SYSRSTn de-assertion 0x0-0x3 = Reserved MPP33 Cpuclk to DDR CLK Ratio0x4 = = Enable Sscg Disable= Disable PCI Express Clock 100 MHz Differential Clock Configuration Pin Configuration Function MPP18 Reserved 88F6281 Hardware Specifications Reset ConfigurationSerial ROM Initialization Serial ROM Data Structure Serial ROM Initialization Operation Boot Sequence 88F6281 Hardware Specifications TAP Controller Jtag InterfaceInstruction Register Jtag Interface Jtag Scan Chain Bypass RegisterID Register Idcode Register Map Electrical Specifications Preliminary Electrical Specifications PreliminaryAbsolute Maximum Ratings Absolute Maximum Ratings 125 Case temperature 88F6281 Hardware Specifications Absolute Maximum Ratings125 Storage temperature RTC interface Recommended Operating Conditions Recommended Operating ConditionsParameter Min Typ Max Units Comments MPP, TWSI, JTAG, SDIO, I 2S, SPI Back-up mode Analog supply for RTC in Battery105 Junction Temperature Internal clock inverter for crystal Thermal Power Dissipation Thermal Power Dissipation Current Consumption Interface Symbol Test Conditions Max UnitsCurrent Consumption CPU @ 1000 MHz General 3.3V Cmos DC Electrical Specifications DC Electrical SpecificationsElectrical Specifications General 3.3V Interface Cmos DC Electrical Specifications 35*VDDIO Input high level Rgmii 1.8V Interface Cmos DC Electrical SpecificationsVIH 65*VDDIO Sdram DDR2 Interface DC Electrical Specifications Sdram DDR2 Interface DC Electrical SpecificationsRTT SPI Interface 3.3V DC Electrical Specifications Twsi Interface 3.3V DC Electrical SpecificationsFollowing table, Vddio means the Vddo power rail Following table Vddio means the Vddo power rail TDM Interface 3.3V DC Electrical Specifications Reference Clock AC Timing Specifications AC Electrical SpecificationsReference Clock AC Timing Specifications SMI Master Mode Reference Clock Description Symbol Min Max Units Tdmspi Output ClockTwsi Master Mode Reference Clock Tclk Sdram DDR2 Interface AC Timing MHz @ Description Symbol Min MaxSdram DDR2 Interface AC Timing Table Sdram DDR2 Interface AC Timing Table Sdram DDR2 Interface Address Timing Table MHz @ Description Symbol Min Max Units Sdram DDR2 Clock Specifications Sdram DDR2 Clock SpecificationsDescription Symbol Min Max Units Sdram DDR2 Interface Test Circuit Sdram DDR2 Interface AC Timing DiagramsVTT CLK Control AddressDQSn TDSI tDHI Rgmii AC Timing Table Reduced Gigabit Media Independent Interface Rgmii AC TimingRgmii 10/100/1000 AC Timing Table at Rgmii 10/100 AC Timing Table at Rgmii Test Circuit Rgmii AC Timing Diagram Gigabit Media Independent Interface Gmii AC Timing 125 MHz Description Symbol Min MaxGmii AC Timing Table Gmii Test Circuit TSETUP Hold Gmii AC Timing DiagramsVILmax TLOW THIGH 5.2 MII/MMII MAC Mode Test Circuit 5.1 MII/MMII MAC Mode AC Timing Table5.3 MII/MMII MAC Mode AC Timing Diagrams MII/MMII MAC Mode AC Timing Table MII/MMII MAC Mode Input AC Timing Diagram SMI Master Mode Test Circuit SMI Master Mode AC Timing TableSMI Master Mode AC Timing Table Serial Management Interface SMI AC Timing MDC SMI Master Mode AC Timing Diagrams Jtag Interface AC Timing 30 MHz Description Symbol Min Max UnitsJtag Interface AC Timing Table Jtag Interface Test Circuit Jtag Interface Output Delay AC Timing Diagram Jtag Interface AC Timing Diagrams 100 kHz Description Symbol Two-Wire Serial Interface Twsi AC TimingTwsi AC Timing Table Twsi Master AC Timing Table Twsi Test Circuit Twsi AC Timing Diagrams 9.1 S/PDIF AC Timing Table Sony/Philips Digital Interconnect Format S/PDIF AC TimingPdif AC Timing Table Pdif Test Circuit 9.2 S/PDIF Test Circuit Inter-IC Sound I2S AC Timing Table Inter-IC Sound Interface I2S AC TimingInter-IC Sound I2S Test Circuit Inter-IC Sound I2S AC Timing Table Inter-IC Sound I2S Output Delay AC Timing Diagram Inter-IC Sound I2S AC Timing Diagrams Time Division Multiplexing TDM Interface AC Timing 192 MHz Description Symbol Min Max UnitsTDM Interface AC Timing Table TDM Interface Test Circuit Pclk DTX TDM Interface Timing DiagramsPclk DRX SPI Master Mode Test Circuit SPI Master Mode AC Timing TableSPI Master Mode AC Timing Table Description Symbol Min Max TCH tCL SPI Master Mode Timing DiagramsSclk Data Out TDOVmin TDOVmax TCSB TCSA Secure Digital Input/Output Sdio Interface AC Timing Sdio Host in High Speed Mode AC Timing TableSecure Digital Input/Output Sdio AC Timing Table Secure Digital Input/Output Sdio Test Circuit Sdio Host in High Speed Mode Output AC Timing Diagram Secure Digital Input/Output Sdio AC Timing Diagrams Transport Stream Interface AC Timing Table Transport Stream TS Interface AC TimingTransport Stream Output Interface AC Timing Table Transport Stream Input Interface AC Timing Table Transport Stream Interface Test Circuit Transport Stream Interface Timing Diagrams Transport Stream Input Interface AC Timing Diagram Differential Interface Reference Clock Characteristics Differential Interface Electrical CharacteristicsClock frequency FCK 100.0 PCI Express Interface Spread Spectrum Requirements Symbol Min Max UnitsFmod 33.0 PCI Express Interface Driver and Receiver Characteristics PCI Express Interface Electrical CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test Circuit Sata Interface Electrical Characteristics TJ5 RlodDJ5 Rlid Differential return loss 3.0 GHz-5.0 GHz Differential return loss 600 MHz-2.4 GHz275.0 750.0 Differential return loss 150 MHz-300 MHz 18.0 Differential return loss 300 MHz-600 MHz USB Driver and Receiver Characteristics USB Electrical CharacteristicsUSB Low Speed Driver and Receiver Characteristics Low Speed Description Sym bol Min Max Units Min Max Full Speed Description High Speed Description Symbol Min Max USB High Speed Driver and Receiver CharacteristicsUSB Interface Driver Waveforms High Speed TX Eye Diagram Pattern Template Thermal Data Preliminary Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/sThermal Data Preliminary Package Hsbga 288-pin Package and Dimensions Symbol Common Dimension Millimeters Package Hsbga 288-pin Package DimensionsPackage Hsbga Part Order Numbering Part Order Numbering/Package Marking88F6281 -xx-BIA2Cxxx-xxxx 88F6281 Part Order Options Part Order Numbering/Package Marking Package Marking Revision Date Comments Revision History Revision History , Power Pin Assignments, on Revised , Reference Clock AC Timing Specifications, on , Current Consumption, on page 80 added the following January 28 Initial release This page is Intentionally Left Blank Page Marvell. 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