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Marvel Group 88F6281 7.3 Bypass Register, 7.4 JTAG Scan Chain, 7.5 ID Register

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88F6281

Hardware Specifications

Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell

Page 74 Document Classification: Proprietary Information December 2, 2008, Preliminary

7.3 Bypass Register

The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR

holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI

input pin is shifted out one cycle later on the TDO output pin. The Bypass register is loaded with 0

when the TAP FSM is in the Capture-DR state.

7.4 JTAG Scan Chain

The JTAG Scan Chain is a serial shift register used to sample and drive all of the device pins during

the JTAG tests. It is a 2-bit per pin shift register in the device, thereby allowing the shift register to

sequentially access all of the data pins both for driving and strobing data. For further details, refer to

the BSDL Description file for the device.

7.5 ID Register

The ID register is a 32-bit deep serial shift register. The ID register is loaded with vendor and device

information when the TAP FSM is in the Capture-DR state. The Identification code format of the ID

register is shown in Tabl e 34, which describes the various ID Code fields.

Table 34: IDCODE Register Map

Bits Value Description

31:28 0x0 Version (4'b0010 for version A0, 4'b0011 for A1, etc.)

27:12 0x6281 Part number

11:1 0x1AB Manufacturer ID

0 1 Mandatory

Contents

Main 88F6281 Integrated Controller Hardware Specifications Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status 88F6281 Integrated Controller XOR Engine Hardware Specifications PRODUCT OVERVIEW FEATURES Page Page Features 88F6281 x16 x8 TDM Usage Model Example: VoIP Gateway Table of Contents Page 88F6281 List of Tables List of Tables Page List of Figures 88F6281 Preface Preface About this Document Related Documentation See the Marvell Extranet website for the latest product documentation. Document Conventions The following conventions are used in this document: Page 88F6281 RTC 1.1 Pin Logic PCI Express MPP JTAG SATA0/1 1.2 Pin Descriptions Table 1: Pin Functions and Assignments Table Key Table 2: Interface Pin Prefix Codes Page 1.2.1 Power Supply Pins Table 3: Power Pin Assignments 88F6281 Table 3: Power Pin Assignments (Continued) 1.2.2 Miscellaneous Pin Assignment The Miscellaneous signal list contains clock and reset, test, and related signals. Table 4: Miscellaneous Pin Assignments 88F6281 1.2.3 DDR SDRAM Interface Pin Assignments Table 5: DDR SDRAM Interface Pin Assignments Table 5: DDR SDRAM Interface Pin Assignments (Continued) 88F6281 1.2.4 PCI Express Interface Pin Assignments Table 6: PCI Express Interface Pin Assignments 1.2.5 SATA Interface Pin Assignments Table 7: SATA Port Interface Pin Assignment 88F6281 1.2.6 Gigabit Ethernet Port Interface Pin Assignments Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments Page Page Page 88F6281 1.2.7 Serial Management Interface (SMI) Interface Pin Assignments Table 9: Serial Management Interface (SMI) Pin Assignments 1.2.8 USB 2.0 Interface Pin Assignments 88F6281 1.2.9 JTAG Interface Pin Assignment Table 11: JTAG Pin Assignment 1.2.10 Real Time Clock (RTC) Interface Pin Assignments 88F6281 1.2.11 NAND Flash Interface Pin Assignment Table 13: NAND Flash Interface Pin Assignment 1.2.12 MPP Interface Pin Assignment Table 14: MPP Interface Pin Assignment The various functionalities of the MPP pins are detailed in 88F6281 1.2.13 Two-Wire Serial Interface (TWSI) Interface All of the TWSI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment 1.2.14 UART Interface Table 16: UART Port 0/1 Interface Pin Assignment 88F6281 1.2.15 Audio (S/PDIF / I2S) Interface 1. Fs is the audio sample rate. Multiplexing, on page 51). multiplexing option. Table 17: Audio (S/PDIF / I2S) Interface Signal Assignment 1.2.16 Serial Peripheral Interface (SPI) Interface Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment 88F6281 1.2.17 Secure Digital Input/Output (SDIO) Interface All of the SDIO signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment 1.2.18 Time Division Multiplexing (TDM) Interface Multiplexing, on page51). multiplexing option (see Section 4, Pin Multiplexing, on page 51). Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment 88F6281 Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment (Continued) 1.2.19 Transport Stream (TS) Interface Multiplexing, on page51). multiplexing option (see Section 4, Pin Multiplexing ). Table 21: Transport Stream (TS) Interface Signal Assignment 88F6281 Table 21: Transport Stream (TS) Interface Signal Assignment (Continued) 1.2.20 Precise Timing Protocol (PTP) Interface Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment 88F6281 1.3 Internal Pull-up and Pull-down Pins Table 23: Internal Pull-up and Pull-down Pins Unused Interface Strapping 2 Table 24: Unused Interface Strapping 3 To open the attached Excel pin list file, double-click the pin icons below: 4 4.1 Multi-Purpose Pins Functional Summary 88F6281 Table 25: MPP Functionality Multi-Purpose Pins Functional Summary Table 26: MPP Function Summary Table26: MPP Function Summary (Continued) Multi-Purpose Pins Functional Summary Table26: MPP Function Summary (Continued) 88F6281 4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP Table 27: Ethernet Ports Pins Multiplexing 88F6281 Table 27: Ethernet Ports Pins Multiplexing (Continued) 4.3 TSMP (TS Multiplexing Pins) on MPP Table 28: TS Port Pin Multiplexing 88F6281 5 Table29 lists the clocks in the 88F6281. Table 29: 88F6281Clocks Clocking Table 30: Supported Clock Combinations Table 29: 88F6281Clocks (Continued) 5.1 Spread Spectrum Clock Generator (SSCG) 6 Settings 6.1 Power-Up/Down Sequence Requirements 6.1.1 Power-Up Sequence Requirements Table 31: I/O and Core Voltages 6.2 Hardware Reset 6.2.1 Reset Out Signal 6.2.2 Power On Reset (POR) 6.2.3 SYSRSTn Duration Counter 6.3 PCI Express Reset 6.3.1 PCI Express Root Complex Reset 6.3.2 PCI Express Endpoint Reset 6.4 Sheeva CPU TAP Controller Reset 6.5 Pins Sample Configuration Table 32: Reset Configuration Page Pins Sample Configuration 88F6281 6.6 Serial ROM Initialization Figure 3: Serial ROM Data Structure 6.6.1 Serial ROM Data Structure 6.6.2 Serial ROM Initialization Operation Figure 4: Serial ROM Read Example 6.7 Boot Sequence Page JTAG Interface 7 7.1 TAP Controller 7.2 Instruction Register Table 33: Supported JTAG Instructions 88F6281 7.3 Bypass Register 7.4 JTAG Scan Chain 7.5 ID Register Table 34: IDCODE Register Map Absolute Maximum Ratings 8 8.1 Absolute Maximum Ratings The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE. Table 35: Absolute Maximum Ratings 88F6281 Table 35: Absolute Maximum Ratings (Continued) Recommended Operating Conditions 8.2 Recommended Operating Conditions Table 36: Recommended Operating Conditions 88F6281 Table 36: Recommended Operating Conditions (Continued) Caution Operation beyond the recommended operating conditions is neither recommended nor guaranteed. 8.3 Thermal Power Dissipation Table 37: Thermal Power Dissipation 88F6281 8.4 Current Consumption Table 38: Current Consumption L2 @ 333 MHz 8.5 DC Electrical Specifications 8.5.1 General 3.3V (CMOS) DC Electrical Specifications Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications 88F6281 8.5.2 RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications 8.5.3 SDRAM DDR2 Interface DC Electrical Specifications 5.0 = RTT 88F6281 8.5.4 Two-Wire Serial Interface (TWSI) 3.3V DC Electrical In the following table, VDDIO means the VDDO power rail. Table 42: TWSI Interface 3.3V DC Electrical Specifications 8.5.5 Serial Peripheral Interface (SPI) 3.3V DC Electrical In the following table VDDIO means the VDDO power rail. 8.5.6 Time Division Multiplexing (TDM) 3.3V DC Electrical Table 44: TDM Interface 3.3V DC Electrical Specifications 88F6281 8.6 AC Electrical Specifications 8.6.1 Reference Clock AC Timing Specifications Table 45: Reference Clock AC Timing Specifications Table 45: Reference Clock AC Timing Specifications (Continued) 88F6281 8.6.2 SDRAM DDR2 Interface AC Timing 8.6.2.1 SDRAM DDR2 Interface AC Timing Table Table 46: SDRAM DDR2 Interface AC Timing Table Table 47: SDRAM DDR2 Interface Address Timing Table 88F6281 8.6.2.2 SDRAM DDR2 Clock Specifications Table 48: SDRAM DDR2 Clock Specifications 8.6.2.3 SDRAM DDR2 Interface Test Circuit Figure 5: SDRAM DDR2 Interface Test Circuit 8.6.2.4 SDRAM DDR2 Interface AC Timing Diagrams Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram Page 8.6.3 Reduced Gigabit Media Independent Interface (RGMII) AC Timing 8.6.3.1 RGMII AC Timing Table Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V Table 50: RGMII 10/100 AC Timing Table at 3.3V 88F6281 8.6.3.2 RGMII Test Circuit Figure 9: RGMII Test C ircu it 8.6.3.3 RGMII AC Timing Diagram Figure 10: RGMII AC Timing Diagram 8.6.4 Gigabit Media Independent Interface (GMII) AC Timing 8.6.4.1 GMII AC Timing Table Table 51: GMII AC Timing Table 8.6.4.2 GMII Test Circuit Figure 11: GMII Test Circuit 8.6.4.3 GMII AC Timing Diagrams Figure 12: GMII Output AC Timing Diagram Figure 13: GMII Input AC Timing Diagram 8.6.5 Media Independent Interface/Marvell Media Independent Interface (MII/MMII) AC Timing 8.6.5.1 MII/MMII MAC Mode AC Timing Table Table 52: MII/MMII MAC Mode AC Timing Table 8.6.5.2 MII/MMII MAC Mode Test Circuit Figure 14: MII/MMII MAC Mode Test Circuit Page 8.6.6 Serial Management Interface (SMI) AC Timing 8.6.6.1 SMI Master Mode AC Timing Table Table 53: SMI Master Mode AC Timing Table 8.6.6.2 SMI Master Mode Test Circuit Figure 17: MDIO Master Mode Test Circuit 8.6.6.3 SMI Master Mode AC Timing Diagrams 8.6.7 JTAG Interface AC Timing 8.6.7.1 JTAG Interface AC Timing Table Table 54: JTAG Interface AC Timing Table 8.6.7.2 JTAG Interface Test Circuit Figure 21: JTAG Interface Test Circuit 8.6.7.3 JTAG Interface AC Timing Diagrams 8.6.8 Two-Wire Serial Interface (TWSI) AC Timing 8.6.8.1 TWSI AC Timing Table Table 55: TWSI Master AC Timing Table Table 56: TWSI Slave AC Timing Table 88F6281 8.6.8.2 TWSI Test Circuit RL CL Figure 24: 8.6.8.3 TWSI AC Timing Diagrams 8.6.9 Sony/Philips Digital Interconnect Format (S/PDIF) AC Timing 8.6.9.1 S/PDIF AC Timing Table Table 57: S/PDIF AC Timing Table 8.6.9.2 S/PDIF Test Circuit 8.6.10 Inter-IC Sound Interface (I2S) AC Timing 8.6.10.1 Inter-IC Sound (I2S) AC Timing Table Table 58: Inter-IC Sound (I2S) AC Timing Table 8.6.10.2 Inter-IC Sound (I2S) Test Circuit Figure 28: Inter-IC Sound (I2S) Test Circuit 8.6.10.3 Inter-IC Sound (I2S) AC Timing Diagrams Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram 8.6.11 Time Division Multiplexing (TDM) Interface AC Timing 8.6.11.1 TDM Interface AC Timing Table Test Point CL Figure 31: TDM Interface Test Circuit 8.6.11.3 TDM Interface Timing Diagrams 8.6.12 Serial Peripheral Interface (SPI) AC Timing 8.6.12.1 SPI (Master Mode) AC Timing Table Test Point CL Table 60: SPI (Master Mode) AC Timing Table 8.6.12.3 SPI (Master Mode) Timing Diagrams Figure 35: SPI (Master Mode) Output AC Timing Diagram Figure 36: SPI (Master Mode) Input AC Timing Diagram SCLK Data in tHD 8.6.13 Secure Digital Input/Output (SDIO) Interface AC Timing 8.6.13.1 Secure Digital Input/Output (SDIO) AC Timing Table Table 61: SDIO Host in High Speed Mode AC Timing Table 8.6.13.2 Secure Digital Input/Output (SDIO) Test Circuit Figure 37: Secure Digital Input/Output (SDIO) Test Circuit 8.6.13.3 Secure Digital Input/Output (SDIO) AC Timing Diagrams Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram 8.6.14 Transport Stream (TS) Interface AC Timing 8.6.14.1 Transport Stream Interface AC Timing Table Table 62: Transport Stream Output Interface AC Timing Table Table 63: Transport Stream Input Interface AC Timing Table 8.6.14.2 Transport Stream Interface Test Circuit 8.6.14.3 Transport Stream Interface Timing Diagrams Figure 42: Transport Stream Input Interface AC Timing Diagram 88F6281 8.7 Differential Interface Electrical Characteristics 8.7.1 Differential Interface Reference Clock Characteristics 8.7.1.1 PCI Express Interface Differential Reference Clock Characteristics Table 64: PCI Express Interface Differential Reference Clock Characteristics PCI Express Interface Spread Spectrum Requirements 88F6281 8.7.2 PCI Express Interface Electrical Characteristics 8.7.2.1 PCI Express Interface Driver and Receiver Characteristics Table 66: PCI Express Interface Driver and Receiver Characteristics 8.7.2.2 PCI Express Interface Test Circuit Figure 43: PCI Express Interface Test Circuit 8.7.3 SATA Interface Electrical Characteristics 8.7.3.1 SATA-I Interface Gen1i Mode Driver and Receiver Characteristics Table 67: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics 88F6281 8.7.3.2 SATA-II Interface Gen2i Mode Driver and Receiver Characteristics Table 68: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics 8.7.4 USB Electrical Characteristics 8.7.4.1 USB Driver and Receiver Characteristics Table 69: USB Low Speed Driver and Receiver Characteristics 88F6281 Table 70: USB Full Speed Driver and Receiver Characteristics Table 71: USB High Speed Driver and Receiver Characteristics 8.7.4.2 USB Interface Driver Waveforms Figure 44: Low/Full Speed Data Signal Rise and Fall Time 88F6281 Figure 45: High Speed TX Eye Diagram Pattern Template Figure 46: High Speed RX Eye Diagram Pattern Template Thermal Data (Preliminary) 9 Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary) 10 Package Table 73: HSBGA 288-pin Package Dimensions 88F6281 11 11.1 Part Order Numbering Figure 48: Sample Part Number xxBIA2Cxxxxxxx 11.2 Package Marking Figure 49 shows a sample Commercial package marking and pin 1 location for the 88F6281. Figure 49: Commercial Package Marking and Pin 1 Location 88F6-BIAe Lot Number YYWW xx@ Country of Origin 88F6281-xx XXXX A Table 75: Revision History Page Page Revision History A January 28, 2008 Initial release