Marvel Group 88F6281 specifications Inter-IC Sound I2S Test Circuit 107

	88F6281
	Hardware Specifications
	Figure 28: Inter-IC Sound (I2S) Test Circuit	107
	Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram	108
	Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram	108
	Figure 31: TDM Interface Test Circuit	109
	Figure 32: TDM Interface Output Delay AC Timing Diagram	110
	Figure 33: TDM Interface Input Delay AC Timing Diagram	110
	Figure 34: SPI (Master Mode) Test Circuit	111
	Figure 35: SPI (Master Mode) Output AC Timing Diagram	112
	Figure 36: SPI (Master Mode) Input AC Timing Diagram	112
	Figure 37: Secure Digital Input/Output (SDIO) Test Circuit	113
	Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram	114
	Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram	114
	Figure 40: Transport Stream Interface Test Circuit	116
	Figure 41: Transport Stream Output Interface AC Timing Diagram	116
	Figure 42: Transport Stream Input Interface AC Timing Diagram	117
	Figure 43: PCI Express Interface Test Circuit	121
	Figure 44: Low/Full Speed Data Signal Rise and Fall Time	127
	Figure 45: High Speed TX Eye Diagram Pattern Template	128
	Figure 46: High Speed RX Eye Diagram Pattern Template	128
9	Thermal Data (Preliminary)	129
10	Package	130
	Figure 47: HSBGA 288-pin Package and Dimensions	130
11 Part Order Numbering/Package Marking		132
	Figure 48: Sample Part Number	132
	Figure 49: Commercial Package Marking and Pin 1 Location	133

Doc. No. MV-S104859-U0 Rev. E		Copyright © 2008 Marvell
Page 14	Document Classification: Proprietary Information	December 2, 2008, Preliminary