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Marvel Group 88F6281 specifications Sony/Philips Digital Interconnect Format S/PDIF AC Timing

Models: 88F6281

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Electrical Specifications

AC Electrical Specifications

8.6.9Sony/Philips Digital Interconnect Format (S/PDIF) AC Timing

8.6.9.1S/PDIF AC Timing Table

Table 57: S/PDIF AC Timing Table

Description	Symbol	Min	Max	Units	Notes
Output frequency accuracy	Ftxtol	-50.0	50.0	ppm	1
Input frequency accuracy	Frxtol	-100.0	100.0	ppm	-
Output jitter - total peak-to-peak	Txjit	-	0.05	UI	1, 2
Jitter transfer gain	Txjitgain	-	3.0	dB	3
		-	10.0	UI	4
Input jitter - total peak-to-peak	Rxjit	-	0.25	UI	5
		-	0.2	UI	6

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

General comment: For more information, refer to the Digital Audio Interface - Part 3: Consumer Applications, IEC 60958-3:2003(E), Chapter 7.3, January 2003.

1.For all signals, the load is CL = 10 pF.

2.Using inristic jitter filter.

3.Refer to Figure-8 in IEC 60958-3:2003(E), Chapter 7.3, January 2003.

4.Defined for up to 5 Hz.

5.Defined from 200 Hz to 400 kHz.

6.Defined for above 400 kHz.

Note

For additional information about working with a coax connection, see the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide.

Copyright © 2008 Marvell		Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary	Document Classification: Proprietary Information	Page 105

Image 105

Marvel Group 88F6281 specifications Sony/Philips Digital Interconnect Format S/PDIF AC Timing, 9.1 S/PDIF AC Timing Table

Contents

88F6281 Hardware Specifications88F6281 Hardware Specifications Document Conventions Document StatusDoc Status Preliminary Technical Publication Hardware Specifications 88F6281Integrated Controller High-performance CPU core, running at up to FeaturesSupports Ieee 802.1Qav draft Audio Video Bridging networks FeaturesBit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHz GbE Port 0 in Gmii mode or GbE PortTDM X16Table of Contents 129 Table of Contents130 132Clocking List of TablesList of Tables Hsbga 288-pin Package Dimensions 131 88F6281 Part Order Options 132Revision History 134 List of Figures Pin and Signal DescriptionsInter-IC Sound I2S Test Circuit 107 About this Document Related DocumentationPreface Following conventions are used in this document Document ConventionsPin and Signal Descriptions Pin Logic PowerFlash Misc PCI ExpressPin Functions and Assignments Table Key Pin DescriptionsInterface Pin Prefix Codes Term DefinitionRTC 88F6281 Hardware Specifications Interface Pin Prefix CodesMPP Twsi Uart SPI Sdio TDM PTPPower Supply Pins Power Pin AssignmentsPin Name Description Type 88F6281 Hardware Specifications Power Pin Assignments Pin Name Power Description Type Rail Miscellaneous Pin AssignmentMiscellaneous Pin Assignments DDR Sdram Interface Pin Assignments DDR Sdram Interface Pin AssignmentsMclkout Sstl Vddm Mcke Sstl VddmMstart Sstl Vddm Mstartburst Sstl VddmBurstin Mpcal MncalPCI Express Interface Pin Assignments PCI Express Interface Pin AssignmentsPin Name Power Rail Description Type Sata Interface Pin AssignmentsSata Port Interface Pin Assignment Pin Name Type Power Rail Description Gigabit Ethernet Port Interface Pin AssignmentsGigabit Ethernet Port0/1 Interface Pin Assignments Gerxctl Cmos Vddgea Gerxclk Cmos VddgeaCmos Vddgeb MPP2724 Gmii Receive ErrorMII/MMII Collision Detect To any clockGmii Transmit Error MII/MMII Transmit ErrorMII/MMII Receive Error MPP32/GE112Serial Management Interface SMI Pin Assignments Serial Management Interface SMI Interface Pin AssignmentsGemdc Cmos Vddgea Gemdio Cmos VddgeaUSB 2.0 Interface Pin Assignments USB 2.0 Interface Pin AssignmentsUSB 2.0 Data Differential Pair Jtag Pin Assignment Jtag Interface Pin AssignmentRTC Interface Pin Assignments Real Time Clock RTC Interface Pin AssignmentsRtcxin RtcxoutNand Flash Interface Pin Assignment Nand Flash Interface Pin AssignmentNfcle Cmos Vddo Nfale Cmos VddoMPP Interface Pin Assignment MPP Interface Pin AssignmentTwo-Wire Serial Interface Twsi Interface Pin Assignment Two-Wire Serial Interface Twsi InterfaceTwsda Cmos Vddo Twsck Cmos VddoUart Port 0/1 Interface Pin Assignment Uart InterfaceAudio S/PDIF / I2S Interface Audio S/PDIF / I2S Interface Signal AssignmentMultiplexing option Fs is the audio sample ratePin Name Pin Type Power Rail Description Serial Peripheral Interface SPI Interface Signal AssignmentSerial Peripheral Interface SPI Interface SPICSnSecure Digital Input/Output Sdio Interface Sdclk Cmos VddoSdcmd Cmos Vddo Time Division Multiplexing TDM Interface Time Division Multiplexing TDM Interface Signal AssignmentTdmspimiso Cmos Vddo Tdmspimosi Cmos VddoTransport Stream TS Interface Transport Stream TS Interface Signal AssignmentTSMP8 Cmos Vddo TSMP7 Cmos VddoTSMP9 Cmos Vddo Cmos Vddo TS0DATA6 VddgebPrecise Timing Protocol PTP Interface Precise Timing Protocol PTP Interface Signal AssignmentPtpclk Cmos Vddo Ptpeventreq Cmos VddoInternal Pull-up and Pull-down Pins Internal Pull-up and Pull-down PinsPin Name Pin Number Pull up/Pull down Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 pin list is provided as an Excel file attachment 88F6281 Pin Map and Pin ListMulti-Purpose Pins Functional Summary Pin MultiplexingPin Multiplexing MPP190 MPP3520 MPP4936 MPP FunctionalityGpio Sata LEDs Audio Nand flash GbESysrsto Spimosi MPP Function SummaryMPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Ethernet Ports Pins Multiplexing Gigabit Ethernet GbE Pins Multiplexing on MPPMPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 TS Port Pin Multiplexing Tsmp TS Multiplexing Pins on MPP88F6281Clocks ClockingLists the clocks in the 88F6281 Clock Type DescriptionSupported Clock Combinations Clocking 88F6281ClocksSata PHY PLL PtpclkSpread Spectrum Clock Generator Sscg 88F6192, and 88F6281 Functional SpecificationsPower-Up/Down Sequence Requirements System Power Up/Down and Reset SettingsPower-Up Sequence Requirements System Power Up/Down and Reset SettingsHardware Reset Power-Down Sequence Requirements88F6281 Power On Reset POR Reset Out SignalMay reset all settings to the factory default values SYSRSTn Duration CounterSheeva CPU TAP Controller Reset PCI Express ResetPins Sample Configuration PCI Express Root Complex ResetReset Configuration Pin Configuration FunctionThan the third Tclk cycle after SYSRSTn de-assertion MPP33 Cpuclk to DDR CLK Ratio 0x0-0x3 = Reserved0x4 = = Enable Sscg Disable= Disable PCI Express Clock 100 MHz Differential Clock ConfigurationPin Configuration Function MPP18 Reserved 88F6281 Hardware Specifications Reset ConfigurationSerial ROM Initialization Serial ROM Data StructureSerial ROM Initialization Operation Boot Sequence88F6281 Hardware Specifications TAP Controller Jtag InterfaceInstruction Register Jtag InterfaceJtag Scan Chain Bypass RegisterID Register Idcode Register MapElectrical Specifications Preliminary Electrical Specifications PreliminaryAbsolute Maximum Ratings Absolute Maximum Ratings125 Case temperature 88F6281 Hardware Specifications Absolute Maximum Ratings125 Storage temperature RTC interfaceRecommended Operating Conditions Recommended Operating ConditionsParameter Min Typ Max Units Comments MPP, TWSI, JTAG, SDIO, I 2S, SPIBack-up mode Analog supply for RTC in Battery105 Junction Temperature Internal clock inverter for crystalThermal Power Dissipation Thermal Power DissipationCurrent Consumption Interface Symbol Test Conditions Max UnitsCurrent Consumption CPU @ 1000 MHzGeneral 3.3V Cmos DC Electrical Specifications DC Electrical SpecificationsElectrical Specifications General 3.3V Interface Cmos DC Electrical Specifications35*VDDIO Input high level Rgmii 1.8V Interface Cmos DC Electrical SpecificationsVIH 65*VDDIOSdram DDR2 Interface DC Electrical Specifications Sdram DDR2 Interface DC Electrical SpecificationsRTT SPI Interface 3.3V DC Electrical Specifications Twsi Interface 3.3V DC Electrical SpecificationsFollowing table, Vddio means the Vddo power rail Following table Vddio means the Vddo power railTDM Interface 3.3V DC Electrical Specifications AC Electrical Specifications Reference Clock AC Timing SpecificationsReference Clock AC Timing Specifications SMI Master Mode Reference Clock Description Symbol Min Max Units Tdmspi Output ClockTwsi Master Mode Reference Clock TclkSdram DDR2 Interface AC Timing MHz @ Description Symbol Min MaxSdram DDR2 Interface AC Timing Table Sdram DDR2 Interface AC Timing TableSdram DDR2 Interface Address Timing Table MHz @ Description Symbol Min Max UnitsSdram DDR2 Clock Specifications Sdram DDR2 Clock SpecificationsDescription Symbol Min Max Units Sdram DDR2 Interface Test Circuit Sdram DDR2 Interface AC Timing DiagramsVTT CLKAddress ControlDQSn TDSI tDHI Rgmii AC Timing Table Reduced Gigabit Media Independent Interface Rgmii AC TimingRgmii 10/100/1000 AC Timing Table at Rgmii 10/100 AC Timing Table atRgmii Test Circuit Rgmii AC Timing DiagramGigabit Media Independent Interface Gmii AC Timing 125 MHz Description Symbol Min MaxGmii AC Timing Table Gmii Test CircuitTSETUP Hold Gmii AC Timing DiagramsVILmax TLOW THIGH5.2 MII/MMII MAC Mode Test Circuit 5.1 MII/MMII MAC Mode AC Timing Table5.3 MII/MMII MAC Mode AC Timing Diagrams MII/MMII MAC Mode AC Timing TableMII/MMII MAC Mode Input AC Timing Diagram SMI Master Mode Test Circuit SMI Master Mode AC Timing TableSMI Master Mode AC Timing Table Serial Management Interface SMI AC TimingMDC SMI Master Mode AC Timing DiagramsJtag Interface AC Timing 30 MHz Description Symbol Min Max UnitsJtag Interface AC Timing Table Jtag Interface Test CircuitJtag Interface Output Delay AC Timing Diagram Jtag Interface AC Timing Diagrams100 kHz Description Symbol Two-Wire Serial Interface Twsi AC TimingTwsi AC Timing Table Twsi Master AC Timing TableTwsi Test Circuit Twsi AC Timing DiagramsSony/Philips Digital Interconnect Format S/PDIF AC Timing 9.1 S/PDIF AC Timing TablePdif AC Timing Table Pdif Test Circuit 9.2 S/PDIF Test CircuitInter-IC Sound I2S AC Timing Table Inter-IC Sound Interface I2S AC TimingInter-IC Sound I2S Test Circuit Inter-IC Sound I2S AC Timing TableInter-IC Sound I2S Output Delay AC Timing Diagram Inter-IC Sound I2S AC Timing DiagramsTime Division Multiplexing TDM Interface AC Timing 192 MHz Description Symbol Min Max UnitsTDM Interface AC Timing Table TDM Interface Test CircuitTDM Interface Timing Diagrams Pclk DTXPclk DRX SPI Master Mode Test Circuit SPI Master Mode AC Timing TableSPI Master Mode AC Timing Table Description Symbol Min MaxTCH tCL SPI Master Mode Timing DiagramsSclk Data Out TDOVmin TDOVmax TCSB TCSASecure Digital Input/Output Sdio Interface AC Timing Sdio Host in High Speed Mode AC Timing TableSecure Digital Input/Output Sdio AC Timing Table Secure Digital Input/Output Sdio Test CircuitSdio Host in High Speed Mode Output AC Timing Diagram Secure Digital Input/Output Sdio AC Timing DiagramsTransport Stream Interface AC Timing Table Transport Stream TS Interface AC TimingTransport Stream Output Interface AC Timing Table Transport Stream Input Interface AC Timing TableTransport Stream Interface Test Circuit Transport Stream Interface Timing DiagramsTransport Stream Input Interface AC Timing Diagram Differential Interface Electrical Characteristics Differential Interface Reference Clock CharacteristicsClock frequency FCK 100.0 Symbol Min Max Units PCI Express Interface Spread Spectrum RequirementsFmod 33.0 PCI Express Interface Electrical Characteristics PCI Express Interface Driver and Receiver CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test CircuitSata Interface Electrical Characteristics TJ5 RlodDJ5 RlidDifferential return loss 3.0 GHz-5.0 GHz Differential return loss 600 MHz-2.4 GHz275.0 750.0 Differential return loss 150 MHz-300 MHz 18.0 Differential return loss 300 MHz-600 MHzUSB Driver and Receiver Characteristics USB Electrical CharacteristicsUSB Low Speed Driver and Receiver Characteristics Low Speed Description Sym bol Min Max UnitsMin Max Full Speed DescriptionUSB High Speed Driver and Receiver Characteristics High Speed Description Symbol Min MaxUSB Interface Driver Waveforms High Speed TX Eye Diagram Pattern Template Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/s Thermal Data PreliminaryThermal Data Preliminary Package Hsbga 288-pin Package and DimensionsSymbol Common Dimension Millimeters Package Hsbga 288-pin Package DimensionsPackage HsbgaPart Order Numbering Part Order Numbering/Package Marking88F6281 -xx-BIA2Cxxx-xxxx 88F6281 Part Order OptionsPart Order Numbering/Package Marking Package MarkingRevision Date Comments Revision HistoryRevision History , Power Pin Assignments, onRevised , Reference Clock AC Timing Specifications, on , Current Consumption, on page 80 added the following January 28 Initial releaseThis page is Intentionally Left Blank Page Marvell. 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