USB Electrical Characteristics | Marvel Group 88F6281 manual

Electrical Specifications

Differential Interface Electrical Characteristics

8.7.4USB Electrical Characteristics

8.7.4.1USB Driver and Receiver Characteristics

Table 69: USB Low Speed Driver and Receiver Characteristics

			Low Speed
Description		Sym bol	Min		Max	Units	Notes
Baud Rate		BR	1.5			Mbps	-
Baud rate tolerance		Bppm	-15000.0		15000.0	ppm	-
	Driver Parameters
Ouput single ended high		VOH	2.8		3.6	V	1
Ouput single ended low		VOL	0.0		0.3	V	2
Output signal crossover voltage		VCRS	1.3		2.0	V	3
Data fall time		TLR	75.0		300.0	ns	3, 4
Data rise time		TLF	75.0		300.0	ns	3, 4
Rise and fall time matching		TLRFM	80.0		125.0	%	-
Source jitter total: to next transition		TUDJ1	-95.0		95.0	ns	5
Source jitter total: for paired transitions		TUDJ2	-150.0		150.0	ns	5
	Receiver Parameters
Input single ended high		VIH	2.0		-	V	-
Input single ended low		VIL	-		0.8	V	-
Differential input sensitivity		VDI	0.2		-	V	-

Notes:

General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings.

1.Defined w ith 1.425 kilohm pull-up resistor to 3.6V.

2.Defined w ith 14.25 kilohm pull-dow n resistor to ground.

3.See "Data Signal Rise and Fall Time" w aveform.

4.Defined from 10% to 90% for rise time and 90% to 10% for fall time.

5.Including frequency tolerance. Timing difference betw een the differential data signals. Defined at crossover point of differential data signals.

Copyright © 2008 Marvell		Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary	Document Classification: Proprietary Information	Page 125

Image 125

Marvel Group 88F6281 specifications USB Electrical Characteristics, USB Driver and Receiver Characteristics

Contents

88F6281 Hardware Specifications Doc Status Preliminary Technical Publication 88F6281 Hardware SpecificationsDocument Conventions Document Status Integrated Controller Hardware Specifications88F6281 High-performance CPU core, running at up to Features Supports Ieee 802.1Qav draft Audio Video Bridging networks Features Bit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHz GbE Port 0 in Gmii mode or GbE Port TDM X16 Table of Contents 129 Table of Contents130 132 Clocking List of Tables List of Tables Revision History 134 Hsbga 288-pin Package Dimensions 13188F6281 Part Order Options 132 List of Figures Pin and Signal Descriptions Inter-IC Sound I2S Test Circuit 107 Preface About this DocumentRelated Documentation Following conventions are used in this document Document Conventions Pin and Signal Descriptions Pin Logic PowerFlash Misc PCI Express Pin Functions and Assignments Table Key Pin DescriptionsInterface Pin Prefix Codes Term Definition RTC 88F6281 Hardware Specifications Interface Pin Prefix CodesMPP Twsi Uart SPI Sdio TDM PTP Pin Name Description Type Power Supply PinsPower Pin Assignments 88F6281 Hardware Specifications Power Pin Assignments Miscellaneous Pin Assignments Pin Name Power Description Type RailMiscellaneous Pin Assignment DDR Sdram Interface Pin Assignments DDR Sdram Interface Pin AssignmentsMclkout Sstl Vddm Mcke Sstl Vddm Mstart Sstl Vddm Mstartburst Sstl VddmBurstin Mpcal Mncal PCI Express Interface Pin Assignments PCI Express Interface Pin Assignments Sata Port Interface Pin Assignment Pin Name Power Rail Description TypeSata Interface Pin Assignments Gigabit Ethernet Port0/1 Interface Pin Assignments Pin Name Type Power Rail DescriptionGigabit Ethernet Port Interface Pin Assignments Cmos Vddgeb Gerxctl Cmos VddgeaGerxclk Cmos Vddgea MPP2724 Gmii Receive ErrorMII/MMII Collision Detect To any clock Gmii Transmit Error MII/MMII Transmit ErrorMII/MMII Receive Error MPP32/GE112 Serial Management Interface SMI Pin Assignments Serial Management Interface SMI Interface Pin AssignmentsGemdc Cmos Vddgea Gemdio Cmos Vddgea USB 2.0 Data Differential Pair USB 2.0 Interface Pin AssignmentsUSB 2.0 Interface Pin Assignments Jtag Pin Assignment Jtag Interface Pin Assignment RTC Interface Pin Assignments Real Time Clock RTC Interface Pin AssignmentsRtcxin Rtcxout Nand Flash Interface Pin Assignment Nand Flash Interface Pin AssignmentNfcle Cmos Vddo Nfale Cmos Vddo MPP Interface Pin Assignment MPP Interface Pin Assignment Two-Wire Serial Interface Twsi Interface Pin Assignment Two-Wire Serial Interface Twsi InterfaceTwsda Cmos Vddo Twsck Cmos Vddo Uart Port 0/1 Interface Pin Assignment Uart Interface Audio S/PDIF / I2S Interface Audio S/PDIF / I2S Interface Signal AssignmentMultiplexing option Fs is the audio sample rate Pin Name Pin Type Power Rail Description Serial Peripheral Interface SPI Interface Signal AssignmentSerial Peripheral Interface SPI Interface SPICSn Sdcmd Cmos Vddo Secure Digital Input/Output Sdio InterfaceSdclk Cmos Vddo Time Division Multiplexing TDM Interface Time Division Multiplexing TDM Interface Signal Assignment Tdmspimiso Cmos Vddo Tdmspimosi Cmos Vddo Transport Stream TS Interface Transport Stream TS Interface Signal Assignment TSMP8 Cmos Vddo TSMP7 Cmos VddoTSMP9 Cmos Vddo Cmos Vddo TS0DATA6 Vddgeb Precise Timing Protocol PTP Interface Precise Timing Protocol PTP Interface Signal AssignmentPtpclk Cmos Vddo Ptpeventreq Cmos Vddo Pin Name Pin Number Pull up/Pull down Internal Pull-up and Pull-down PinsInternal Pull-up and Pull-down Pins Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 pin list is provided as an Excel file attachment 88F6281 Pin Map and Pin List Pin Multiplexing Multi-Purpose Pins Functional SummaryPin Multiplexing MPP190 MPP3520 MPP4936 MPP FunctionalityGpio Sata LEDs Audio Nand flash GbE Sysrsto Spimosi MPP Function Summary MPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Ethernet Ports Pins Multiplexing Gigabit Ethernet GbE Pins Multiplexing on MPP MPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 TS Port Pin Multiplexing Tsmp TS Multiplexing Pins on MPP 88F6281Clocks ClockingLists the clocks in the 88F6281 Clock Type Description Supported Clock Combinations Clocking 88F6281ClocksSata PHY PLL Ptpclk Spread Spectrum Clock Generator Sscg 88F6192, and 88F6281 Functional Specifications Power-Up/Down Sequence Requirements System Power Up/Down and Reset SettingsPower-Up Sequence Requirements System Power Up/Down and Reset Settings 88F6281 Hardware ResetPower-Down Sequence Requirements Power On Reset POR Reset Out SignalMay reset all settings to the factory default values SYSRSTn Duration Counter Sheeva CPU TAP Controller Reset PCI Express ResetPins Sample Configuration PCI Express Root Complex Reset Than the third Tclk cycle after SYSRSTn de-assertion Reset ConfigurationPin Configuration Function 0x4 = MPP33 Cpuclk to DDR CLK Ratio0x0-0x3 = Reserved = Enable Sscg Disable= Disable PCI Express Clock 100 MHz Differential Clock Configuration Pin Configuration Function MPP18 Reserved 88F6281 Hardware Specifications Reset ConfigurationSerial ROM Initialization Serial ROM Data Structure Serial ROM Initialization Operation Boot Sequence 88F6281 Hardware Specifications TAP Controller Jtag InterfaceInstruction Register Jtag Interface Jtag Scan Chain Bypass RegisterID Register Idcode Register Map Electrical Specifications Preliminary Electrical Specifications PreliminaryAbsolute Maximum Ratings Absolute Maximum Ratings 125 Case temperature 88F6281 Hardware Specifications Absolute Maximum Ratings125 Storage temperature RTC interface Recommended Operating Conditions Recommended Operating ConditionsParameter Min Typ Max Units Comments MPP, TWSI, JTAG, SDIO, I 2S, SPI Back-up mode Analog supply for RTC in Battery105 Junction Temperature Internal clock inverter for crystal Thermal Power Dissipation Thermal Power Dissipation Current Consumption Interface Symbol Test Conditions Max UnitsCurrent Consumption CPU @ 1000 MHz General 3.3V Cmos DC Electrical Specifications DC Electrical SpecificationsElectrical Specifications General 3.3V Interface Cmos DC Electrical Specifications 35*VDDIO Input high level Rgmii 1.8V Interface Cmos DC Electrical SpecificationsVIH 65*VDDIO RTT Sdram DDR2 Interface DC Electrical SpecificationsSdram DDR2 Interface DC Electrical Specifications SPI Interface 3.3V DC Electrical Specifications Twsi Interface 3.3V DC Electrical SpecificationsFollowing table, Vddio means the Vddo power rail Following table Vddio means the Vddo power rail TDM Interface 3.3V DC Electrical Specifications Reference Clock AC Timing Specifications AC Electrical SpecificationsReference Clock AC Timing Specifications SMI Master Mode Reference Clock Description Symbol Min Max Units Tdmspi Output ClockTwsi Master Mode Reference Clock Tclk Sdram DDR2 Interface AC Timing MHz @ Description Symbol Min MaxSdram DDR2 Interface AC Timing Table Sdram DDR2 Interface AC Timing Table Sdram DDR2 Interface Address Timing Table MHz @ Description Symbol Min Max Units Description Symbol Min Max Units Sdram DDR2 Clock SpecificationsSdram DDR2 Clock Specifications Sdram DDR2 Interface Test Circuit Sdram DDR2 Interface AC Timing DiagramsVTT CLK DQSn TDSI tDHI AddressControl Rgmii AC Timing Table Reduced Gigabit Media Independent Interface Rgmii AC TimingRgmii 10/100/1000 AC Timing Table at Rgmii 10/100 AC Timing Table at Rgmii Test Circuit Rgmii AC Timing Diagram Gigabit Media Independent Interface Gmii AC Timing 125 MHz Description Symbol Min MaxGmii AC Timing Table Gmii Test Circuit TSETUP Hold Gmii AC Timing DiagramsVILmax TLOW THIGH 5.2 MII/MMII MAC Mode Test Circuit 5.1 MII/MMII MAC Mode AC Timing Table5.3 MII/MMII MAC Mode AC Timing Diagrams MII/MMII MAC Mode AC Timing Table MII/MMII MAC Mode Input AC Timing Diagram SMI Master Mode Test Circuit SMI Master Mode AC Timing TableSMI Master Mode AC Timing Table Serial Management Interface SMI AC Timing MDC SMI Master Mode AC Timing Diagrams Jtag Interface AC Timing 30 MHz Description Symbol Min Max UnitsJtag Interface AC Timing Table Jtag Interface Test Circuit Jtag Interface Output Delay AC Timing Diagram Jtag Interface AC Timing Diagrams 100 kHz Description Symbol Two-Wire Serial Interface Twsi AC TimingTwsi AC Timing Table Twsi Master AC Timing Table Twsi Test Circuit Twsi AC Timing Diagrams Pdif AC Timing Table Sony/Philips Digital Interconnect Format S/PDIF AC Timing9.1 S/PDIF AC Timing Table Pdif Test Circuit 9.2 S/PDIF Test Circuit Inter-IC Sound I2S AC Timing Table Inter-IC Sound Interface I2S AC TimingInter-IC Sound I2S Test Circuit Inter-IC Sound I2S AC Timing Table Inter-IC Sound I2S Output Delay AC Timing Diagram Inter-IC Sound I2S AC Timing Diagrams Time Division Multiplexing TDM Interface AC Timing 192 MHz Description Symbol Min Max UnitsTDM Interface AC Timing Table TDM Interface Test Circuit Pclk DRX TDM Interface Timing DiagramsPclk DTX SPI Master Mode Test Circuit SPI Master Mode AC Timing TableSPI Master Mode AC Timing Table Description Symbol Min Max TCH tCL SPI Master Mode Timing DiagramsSclk Data Out TDOVmin TDOVmax TCSB TCSA Secure Digital Input/Output Sdio Interface AC Timing Sdio Host in High Speed Mode AC Timing TableSecure Digital Input/Output Sdio AC Timing Table Secure Digital Input/Output Sdio Test Circuit Sdio Host in High Speed Mode Output AC Timing Diagram Secure Digital Input/Output Sdio AC Timing Diagrams Transport Stream Interface AC Timing Table Transport Stream TS Interface AC TimingTransport Stream Output Interface AC Timing Table Transport Stream Input Interface AC Timing Table Transport Stream Interface Test Circuit Transport Stream Interface Timing Diagrams Transport Stream Input Interface AC Timing Diagram Clock frequency FCK 100.0 Differential Interface Electrical CharacteristicsDifferential Interface Reference Clock Characteristics Fmod 33.0 Symbol Min Max UnitsPCI Express Interface Spread Spectrum Requirements PCI Express Interface Driver and Receiver Characteristics PCI Express Interface Electrical CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test Circuit Sata Interface Electrical Characteristics TJ5 RlodDJ5 Rlid Differential return loss 3.0 GHz-5.0 GHz Differential return loss 600 MHz-2.4 GHz275.0 750.0 Differential return loss 150 MHz-300 MHz 18.0 Differential return loss 300 MHz-600 MHz USB Driver and Receiver Characteristics USB Electrical CharacteristicsUSB Low Speed Driver and Receiver Characteristics Low Speed Description Sym bol Min Max Units Min Max Full Speed Description USB Interface Driver Waveforms USB High Speed Driver and Receiver CharacteristicsHigh Speed Description Symbol Min Max High Speed TX Eye Diagram Pattern Template Thermal Data Preliminary Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/sThermal Data Preliminary Package Hsbga 288-pin Package and Dimensions Symbol Common Dimension Millimeters Package Hsbga 288-pin Package DimensionsPackage Hsbga Part Order Numbering Part Order Numbering/Package Marking88F6281 -xx-BIA2Cxxx-xxxx 88F6281 Part Order Options Part Order Numbering/Package Marking Package Marking Revision Date Comments Revision History Revision History , Power Pin Assignments, on Revised , Reference Clock AC Timing Specifications, on , Current Consumption, on page 80 added the following January 28 Initial release This page is Intentionally Left Blank Page Marvell. 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