Marvel Group 88F6281 specifications Boot Sequence, Serial ROM Initialization Operation

System Power Up/Down and Reset Settings

Boot Sequence

The serial ROM initialization logic reads eight bytes at a time. It performs address decoding on the 32-bit address being read, and based on address decoding result, writes the next four bytes to the required target.

The Serial Initialization Last Data Register contains the expected value of last serial data item (default value is 0xFFFFFFFF). When the device reaches last data, it stops the initialization sequence.

6.6.2Serial ROM Initialization Operation

On SYSRSTn de-assertion, the device starts the initialization process. It first performs a dummy write access to the serial ROM, with data byte(s) of 0x0, to set the ROM byte offset to 0x0. Then, it performs the sequence of reads, until it reaches last data item, as shown in Figure 4.

Figure 4: Serial ROM Read Example

s								w	Upper Byte Offset
t								r
a								i
r								t
t								e
s	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0

a	a
c	c
k	k
ROM
Address

s	r	Data from
Lower Byte Offset t
	e	ROM
a
r	a
	d
t

0	0	0	0	0	0	0	0		s	1	0	1	0	0	0	0	1		A	A	A	A	A	A	A	A		A	A	A	A
								a										a									a
								c										c									c
								k										k									k

ROM

Address

Last Data	s
from ROM
	t
	o
	p

1	1	1	1	1	1	1	1		1	1	1	1	1	1	1	1		1	1	1	1	1	1	1	1		1	1	1	1	1	1	1	1		x	x	x	x	x	x	x	x
								a									a									a									a
								c									c									c									c
								k									k									k									k

p

n a c k

For a detailed description of TWSI implementation, see the Two-Wire Serial Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

„Initialization data must be programmed in the serial ROM starting at offset 0x0.

„The device assumes 7-bit serial ROM address of ‘b1010000.

„After receiving the last data identifier (default value is 0xFFFFFFFF), the device receives an additional byte of dummy data. It responds with no-ack and then asserts the stop bit.

„The serial EEPROM must contain two address offset bytes (It must not be less than a 256 byte ROM.).

6.7Boot Sequence

The device requires that SYSRSTn stay asserted for at least 300 μs after power and clocks are stable. The following procedure describes the boot sequence starting with the reset assertion:

1.While SYSRSTn is asserted, the CPU PLL and the core PLL are locked.

2.Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK cycles.

3.If Serial ROM initialization is enabled, an initialization sequence is started.

4.If configured to boot from NAND flash (and BootROM is disabled), the device also performs a NAND Flash boot sequence to prepare page 0 in the NAND flash device for read.

Copyright © 2008 Marvell		Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary	Document Classification: Proprietary Information	Page 71