Pin Name Type Power Rail Description | Marvel Group 88F6281 specs

88F6281

Hardware Specifications

1.2.6Gigabit Ethernet Port Interface Pin Assignments

For additional information about the Gigabit Ethernet port pin functions refer to Section 4.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 57.

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments

Pin Name

I/O

Pin

Type

Power Rail

Description

Port0—Dedicated GbE Pins

GE_TXCLKOUT	t/s	CMOS	VDD_GE_A	RGMII Transmit Clock
	O			RGMII transmit reference output clock for GE_TXD[3:0] and
				GE_TXCTL.
				Provides 125 MHz, 25 MHz or 2.5 MHz clock.
				Not used in MII/MMII mode.

	I			MII/MMII Transmit Clock
				MII/MMII transmit reference clock from PHY.
				Provides the timing reference for the transmission of the MII
				transmit clock, transmit enable, and GE_TXD[3:0] signals. This
				clock operates at 2.5 MHz or 25 MHz.

	t/s			GMII Transmit Clock
	O			Provides the timing reference for the transfer of the transmit
				enable, transmit error and transmit data signals. This clock
				operates at 125 MHz.

GE_TXD[3:0]	t/s	CMOS	VDD_GE_A	RGMII Transmit Data
	O			Contains the transmit data nibble outputs that run at double data
				rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT
				and bits [7:4] driven on the falling edge.

				MII/MMII Transmit Data
				Contains the transmit data nibble outputs that are synchronous
				to the transmit clock input.

				GMII Transmit Data
				Contains the transmit data nibble outputs.

GE_TXCTL	t/s	CMOS	VDD_GE_A	RGMII Transmit Control
	O			Transmit control synchronous to the GE_TXCLKOUT output
				rising/falling edge.
				GE_TXEN is driven on the rising edge of GE_TXCLKOUT.
				A logical derivative of transmit enable and transmit error is driven
				on the falling edge of GE_TXCLKOUT.

				MII/MMII Transmit Enable
				Indicates that the packet is being transmitted to the PHY. It Is
				synchronous to transmit clock.

				GMII Transmit Enable
				Indicates that the packet is being transmitted to the PHY.
				It Is synchronous to GE_TXCLKOUT.

Doc. No. MV-S104859-U0 Rev. E		Copyright © 2008 Marvell
Page 28	Document Classification: Proprietary Information	December 2, 2008, Preliminary

Image 28

Marvel Group 88F6281 Gigabit Ethernet Port Interface Pin Assignments, Gigabit Ethernet Port0/1 Interface Pin Assignments

Contents

Hardware Specifications 88F6281 Document Conventions Document Status 88F6281 Hardware SpecificationsDoc Status Preliminary Technical Publication 88F6281 Hardware SpecificationsIntegrated Controller Features High-performance CPU core, running at up to Features Supports Ieee 802.1Qav draft Audio Video Bridging networks GbE Port 0 in Gmii mode or GbE Port Bit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHz X16 TDM Table of Contents Table of Contents 129130 132 List of Tables Clocking List of Tables 88F6281 Part Order Options 132 Hsbga 288-pin Package Dimensions 131Revision History 134 Pin and Signal Descriptions List of Figures Inter-IC Sound I2S Test Circuit 107 Related Documentation About this DocumentPreface Document Conventions Following conventions are used in this document Pin and Signal Descriptions Power Pin LogicFlash Misc PCI Express Pin Descriptions Pin Functions and Assignments Table KeyInterface Pin Prefix Codes Term Definition 88F6281 Hardware Specifications Interface Pin Prefix Codes RTCMPP Twsi Uart SPI Sdio TDM PTP Power Pin Assignments Power Supply PinsPin Name Description Type 88F6281 Hardware Specifications Power Pin Assignments Miscellaneous Pin Assignment Pin Name Power Description Type RailMiscellaneous Pin Assignments DDR Sdram Interface Pin Assignments DDR Sdram Interface Pin AssignmentsMclkout Sstl Vddm Mcke Sstl Vddm Mstartburst Sstl Vddm Mstart Sstl VddmBurstin Mpcal Mncal PCI Express Interface Pin Assignments PCI Express Interface Pin Assignments Sata Interface Pin Assignments Pin Name Power Rail Description TypeSata Port Interface Pin Assignment Gigabit Ethernet Port Interface Pin Assignments Pin Name Type Power Rail DescriptionGigabit Ethernet Port0/1 Interface Pin Assignments Gerxclk Cmos Vddgea Gerxctl Cmos VddgeaCmos Vddgeb Gmii Receive Error MPP2724MII/MMII Collision Detect To any clock MII/MMII Transmit Error Gmii Transmit ErrorMII/MMII Receive Error MPP32/GE112 Serial Management Interface SMI Interface Pin Assignments Serial Management Interface SMI Pin AssignmentsGemdc Cmos Vddgea Gemdio Cmos Vddgea USB 2.0 Interface Pin Assignments USB 2.0 Interface Pin AssignmentsUSB 2.0 Data Differential Pair Jtag Interface Pin Assignment Jtag Pin Assignment Real Time Clock RTC Interface Pin Assignments RTC Interface Pin AssignmentsRtcxin Rtcxout Nand Flash Interface Pin Assignment Nand Flash Interface Pin AssignmentNfcle Cmos Vddo Nfale Cmos Vddo MPP Interface Pin Assignment MPP Interface Pin Assignment Two-Wire Serial Interface Twsi Interface Two-Wire Serial Interface Twsi Interface Pin AssignmentTwsda Cmos Vddo Twsck Cmos Vddo Uart Interface Uart Port 0/1 Interface Pin Assignment Audio S/PDIF / I2S Interface Signal Assignment Audio S/PDIF / I2S InterfaceMultiplexing option Fs is the audio sample rate Serial Peripheral Interface SPI Interface Signal Assignment Pin Name Pin Type Power Rail DescriptionSerial Peripheral Interface SPI Interface SPICSn Sdclk Cmos Vddo Secure Digital Input/Output Sdio InterfaceSdcmd Cmos Vddo Time Division Multiplexing TDM Interface Signal Assignment Time Division Multiplexing TDM Interface Tdmspimosi Cmos Vddo Tdmspimiso Cmos Vddo Transport Stream TS Interface Signal Assignment Transport Stream TS Interface TSMP7 Cmos Vddo TSMP8 Cmos VddoTSMP9 Cmos Vddo Cmos Vddo TS0DATA6 Vddgeb Precise Timing Protocol PTP Interface Signal Assignment Precise Timing Protocol PTP InterfacePtpclk Cmos Vddo Ptpeventreq Cmos Vddo Internal Pull-up and Pull-down Pins Internal Pull-up and Pull-down PinsPin Name Pin Number Pull up/Pull down Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 Pin Map and Pin List 88F6281 pin list is provided as an Excel file attachment Pin Multiplexing Multi-Purpose Pins Functional SummaryPin Multiplexing MPP Functionality MPP190 MPP3520 MPP4936Gpio Sata LEDs Audio Nand flash GbE MPP Function Summary Sysrsto Spimosi MPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Gigabit Ethernet GbE Pins Multiplexing on MPP Ethernet Ports Pins Multiplexing MPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 Tsmp TS Multiplexing Pins on MPP TS Port Pin Multiplexing Clocking 88F6281ClocksLists the clocks in the 88F6281 Clock Type Description Clocking 88F6281Clocks Supported Clock CombinationsSata PHY PLL Ptpclk 88F6192, and 88F6281 Functional Specifications Spread Spectrum Clock Generator Sscg System Power Up/Down and Reset Settings Power-Up/Down Sequence RequirementsPower-Up Sequence Requirements System Power Up/Down and Reset Settings Power-Down Sequence Requirements Hardware Reset88F6281 Reset Out Signal Power On Reset PORMay reset all settings to the factory default values SYSRSTn Duration Counter PCI Express Reset Sheeva CPU TAP Controller ResetPins Sample Configuration PCI Express Root Complex Reset Pin Configuration Function Reset ConfigurationThan the third Tclk cycle after SYSRSTn de-assertion 0x0-0x3 = Reserved MPP33 Cpuclk to DDR CLK Ratio0x4 = Sscg Disable = Enable= Disable PCI Express Clock 100 MHz Differential Clock Configuration 88F6281 Hardware Specifications Reset Configuration Pin Configuration Function MPP18 ReservedSerial ROM Initialization Serial ROM Data Structure Boot Sequence Serial ROM Initialization Operation 88F6281 Hardware Specifications Jtag Interface TAP ControllerInstruction Register Jtag Interface Bypass Register Jtag Scan ChainID Register Idcode Register Map Electrical Specifications Preliminary Electrical Specifications PreliminaryAbsolute Maximum Ratings Absolute Maximum Ratings 88F6281 Hardware Specifications Absolute Maximum Ratings 125 Case temperature125 Storage temperature RTC interface Recommended Operating Conditions Recommended Operating ConditionsParameter Min Typ Max Units Comments MPP, TWSI, JTAG, SDIO, I 2S, SPI Analog supply for RTC in Battery Back-up mode105 Junction Temperature Internal clock inverter for crystal Thermal Power Dissipation Thermal Power Dissipation Interface Symbol Test Conditions Max Units Current ConsumptionCurrent Consumption CPU @ 1000 MHz DC Electrical Specifications General 3.3V Cmos DC Electrical SpecificationsElectrical Specifications General 3.3V Interface Cmos DC Electrical Specifications Rgmii 1.8V Interface Cmos DC Electrical Specifications 35*VDDIO Input high levelVIH 65*VDDIO Sdram DDR2 Interface DC Electrical Specifications Sdram DDR2 Interface DC Electrical SpecificationsRTT Twsi Interface 3.3V DC Electrical Specifications SPI Interface 3.3V DC Electrical SpecificationsFollowing table, Vddio means the Vddo power rail Following table Vddio means the Vddo power rail TDM Interface 3.3V DC Electrical Specifications Reference Clock AC Timing Specifications AC Electrical SpecificationsReference Clock AC Timing Specifications Description Symbol Min Max Units Tdmspi Output Clock SMI Master Mode Reference ClockTwsi Master Mode Reference Clock Tclk MHz @ Description Symbol Min Max Sdram DDR2 Interface AC TimingSdram DDR2 Interface AC Timing Table Sdram DDR2 Interface AC Timing Table MHz @ Description Symbol Min Max Units Sdram DDR2 Interface Address Timing Table Sdram DDR2 Clock Specifications Sdram DDR2 Clock SpecificationsDescription Symbol Min Max Units Sdram DDR2 Interface AC Timing Diagrams Sdram DDR2 Interface Test CircuitVTT CLK Control AddressDQSn TDSI tDHI Reduced Gigabit Media Independent Interface Rgmii AC Timing Rgmii AC Timing TableRgmii 10/100/1000 AC Timing Table at Rgmii 10/100 AC Timing Table at Rgmii AC Timing Diagram Rgmii Test Circuit 125 MHz Description Symbol Min Max Gigabit Media Independent Interface Gmii AC TimingGmii AC Timing Table Gmii Test Circuit Gmii AC Timing Diagrams TSETUP HoldVILmax TLOW THIGH 5.1 MII/MMII MAC Mode AC Timing Table 5.2 MII/MMII MAC Mode Test Circuit5.3 MII/MMII MAC Mode AC Timing Diagrams MII/MMII MAC Mode AC Timing Table MII/MMII MAC Mode Input AC Timing Diagram SMI Master Mode AC Timing Table SMI Master Mode Test CircuitSMI Master Mode AC Timing Table Serial Management Interface SMI AC Timing SMI Master Mode AC Timing Diagrams MDC 30 MHz Description Symbol Min Max Units Jtag Interface AC TimingJtag Interface AC Timing Table Jtag Interface Test Circuit Jtag Interface AC Timing Diagrams Jtag Interface Output Delay AC Timing Diagram Two-Wire Serial Interface Twsi AC Timing 100 kHz Description SymbolTwsi AC Timing Table Twsi Master AC Timing Table Twsi AC Timing Diagrams Twsi Test Circuit 9.1 S/PDIF AC Timing Table Sony/Philips Digital Interconnect Format S/PDIF AC TimingPdif AC Timing Table 9.2 S/PDIF Test Circuit Pdif Test Circuit Inter-IC Sound Interface I2S AC Timing Inter-IC Sound I2S AC Timing TableInter-IC Sound I2S Test Circuit Inter-IC Sound I2S AC Timing Table Inter-IC Sound I2S AC Timing Diagrams Inter-IC Sound I2S Output Delay AC Timing Diagram 192 MHz Description Symbol Min Max Units Time Division Multiplexing TDM Interface AC TimingTDM Interface AC Timing Table TDM Interface Test Circuit Pclk DTX TDM Interface Timing DiagramsPclk DRX SPI Master Mode AC Timing Table SPI Master Mode Test CircuitSPI Master Mode AC Timing Table Description Symbol Min Max SPI Master Mode Timing Diagrams TCH tCLSclk Data Out TDOVmin TDOVmax TCSB TCSA Sdio Host in High Speed Mode AC Timing Table Secure Digital Input/Output Sdio Interface AC TimingSecure Digital Input/Output Sdio AC Timing Table Secure Digital Input/Output Sdio Test Circuit Secure Digital Input/Output Sdio AC Timing Diagrams Sdio Host in High Speed Mode Output AC Timing Diagram Transport Stream TS Interface AC Timing Transport Stream Interface AC Timing TableTransport Stream Output Interface AC Timing Table Transport Stream Input Interface AC Timing Table Transport Stream Interface Timing Diagrams Transport Stream Interface Test Circuit Transport Stream Input Interface AC Timing Diagram Differential Interface Reference Clock Characteristics Differential Interface Electrical CharacteristicsClock frequency FCK 100.0 PCI Express Interface Spread Spectrum Requirements Symbol Min Max UnitsFmod 33.0 PCI Express Interface Driver and Receiver Characteristics PCI Express Interface Electrical CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test Circuit Sata Interface Electrical Characteristics Rlod TJ5DJ5 Rlid Differential return loss 600 MHz-2.4 GHz Differential return loss 3.0 GHz-5.0 GHz275.0 750.0 Differential return loss 150 MHz-300 MHz 18.0 Differential return loss 300 MHz-600 MHz USB Electrical Characteristics USB Driver and Receiver CharacteristicsUSB Low Speed Driver and Receiver Characteristics Low Speed Description Sym bol Min Max Units Full Speed Description Min Max High Speed Description Symbol Min Max USB High Speed Driver and Receiver CharacteristicsUSB Interface Driver Waveforms High Speed TX Eye Diagram Pattern Template Thermal Data Preliminary Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/sThermal Data Preliminary Hsbga 288-pin Package and Dimensions Package Package Hsbga 288-pin Package Dimensions Symbol Common Dimension MillimetersPackage Hsbga Part Order Numbering/Package Marking Part Order Numbering88F6281 -xx-BIA2Cxxx-xxxx 88F6281 Part Order Options Package Marking Part Order Numbering/Package Marking Revision History Revision Date Comments , Power Pin Assignments, on Revision History Revised , Reference Clock AC Timing Specifications, on January 28 Initial release , Current Consumption, on page 80 added the following This page is Intentionally Left Blank Page Marvell. Moving Forward Faster