Secure Digital Input/Output Sdio Interface

88F6281

Hardware Specifications

1.2.17Secure Digital Input/Output (SDIO) Interface

				All of the SDIO signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing,

				on page 51).
	Note			on page 51).
	Note

Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment

Pin Name	I/O	Pin Type	Power Rail	Description
SD_CLK	O	CMOS	VDDO	SDIO Clock
SD_CMD	I/O	CMOS	VDDO	SDIO Command
				Used to transfer a command serially from the SDIO host to the
				SDIO device. Used to transfer a command response serially
				from the SDIO device to the SDIO host.
				NOTE: This pin requires a pull up on board.
SD_D[3:0]	I/O	CMOS	VDDO	SDIO Data Input/Output
				Used to transfer data from the SDIO host to the SDIO device or
				vice versa.
				NOTE: These pins require a pull up on board.

Doc. No. MV-S104859-U0 Rev. E		Copyright © 2008 Marvell
Page 42	Document Classification: Proprietary Information	December 2, 2008, Preliminary

Page 42

Image 42

Marvel Group 88F6281 specifications Secure Digital Input/Output Sdio Interface, Sdclk Cmos Vddo, Sdcmd Cmos Vddo

Contents

Hardware Specifications 88F6281 88F6281 Hardware Specifications Document Conventions Document StatusDoc Status Preliminary Technical Publication Hardware Specifications 88F6281Integrated Controller Features High-performance CPU core, running at up to Features Supports Ieee 802.1Qav draft Audio Video Bridging networks GbE Port 0 in Gmii mode or GbE Port Bit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHz X16 TDM Table of Contents 130 Table of Contents129 132 List of Tables Clocking List of Tables Hsbga 288-pin Package Dimensions 131 88F6281 Part Order Options 132Revision History 134 Pin and Signal Descriptions List of Figures Inter-IC Sound I2S Test Circuit 107 About this Document Related DocumentationPreface Document Conventions Following conventions are used in this document Pin and Signal Descriptions Flash PowerPin Logic Misc PCI Express Interface Pin Prefix Codes Pin DescriptionsPin Functions and Assignments Table Key Term Definition MPP Twsi Uart 88F6281 Hardware Specifications Interface Pin Prefix CodesRTC SPI Sdio TDM PTP Power Supply Pins Power Pin AssignmentsPin Name Description Type 88F6281 Hardware Specifications Power Pin Assignments Pin Name Power Description Type Rail Miscellaneous Pin AssignmentMiscellaneous Pin Assignments Mclkout Sstl Vddm DDR Sdram Interface Pin AssignmentsDDR Sdram Interface Pin Assignments Mcke Sstl Vddm Burstin Mpcal Mstartburst Sstl VddmMstart Sstl Vddm Mncal PCI Express Interface Pin Assignments PCI Express Interface Pin Assignments Pin Name Power Rail Description Type Sata Interface Pin AssignmentsSata Port Interface Pin Assignment Pin Name Type Power Rail Description Gigabit Ethernet Port Interface Pin AssignmentsGigabit Ethernet Port0/1 Interface Pin Assignments Gerxctl Cmos Vddgea Gerxclk Cmos VddgeaCmos Vddgeb MII/MMII Collision Detect Gmii Receive ErrorMPP2724 To any clock MII/MMII Receive Error MII/MMII Transmit ErrorGmii Transmit Error MPP32/GE112 Gemdc Cmos Vddgea Serial Management Interface SMI Interface Pin AssignmentsSerial Management Interface SMI Pin Assignments Gemdio Cmos Vddgea USB 2.0 Interface Pin Assignments USB 2.0 Interface Pin AssignmentsUSB 2.0 Data Differential Pair Jtag Interface Pin Assignment Jtag Pin Assignment Rtcxin Real Time Clock RTC Interface Pin AssignmentsRTC Interface Pin Assignments Rtcxout Nfcle Cmos Vddo Nand Flash Interface Pin AssignmentNand Flash Interface Pin Assignment Nfale Cmos Vddo MPP Interface Pin Assignment MPP Interface Pin Assignment Twsda Cmos Vddo Two-Wire Serial Interface Twsi InterfaceTwo-Wire Serial Interface Twsi Interface Pin Assignment Twsck Cmos Vddo Uart Interface Uart Port 0/1 Interface Pin Assignment Multiplexing option Audio S/PDIF / I2S Interface Signal AssignmentAudio S/PDIF / I2S Interface Fs is the audio sample rate Serial Peripheral Interface SPI Interface Serial Peripheral Interface SPI Interface Signal AssignmentPin Name Pin Type Power Rail Description SPICSn Secure Digital Input/Output Sdio Interface Sdclk Cmos VddoSdcmd Cmos Vddo Time Division Multiplexing TDM Interface Signal Assignment Time Division Multiplexing TDM Interface Tdmspimosi Cmos Vddo Tdmspimiso Cmos Vddo Transport Stream TS Interface Signal Assignment Transport Stream TS Interface TSMP9 Cmos Vddo TSMP7 Cmos VddoTSMP8 Cmos Vddo Cmos Vddo TS0DATA6 Vddgeb Ptpclk Cmos Vddo Precise Timing Protocol PTP Interface Signal AssignmentPrecise Timing Protocol PTP Interface Ptpeventreq Cmos Vddo Internal Pull-up and Pull-down Pins Internal Pull-up and Pull-down PinsPin Name Pin Number Pull up/Pull down Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 Pin Map and Pin List 88F6281 pin list is provided as an Excel file attachment Multi-Purpose Pins Functional Summary Pin MultiplexingPin Multiplexing Gpio MPP FunctionalityMPP190 MPP3520 MPP4936 Sata LEDs Audio Nand flash GbE MPP Function Summary Sysrsto Spimosi MPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Gigabit Ethernet GbE Pins Multiplexing on MPP Ethernet Ports Pins Multiplexing MPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 Tsmp TS Multiplexing Pins on MPP TS Port Pin Multiplexing Lists the clocks in the 88F6281 Clocking88F6281Clocks Clock Type Description Sata PHY PLL Clocking 88F6281ClocksSupported Clock Combinations Ptpclk 88F6192, and 88F6281 Functional Specifications Spread Spectrum Clock Generator Sscg Power-Up Sequence Requirements System Power Up/Down and Reset SettingsPower-Up/Down Sequence Requirements System Power Up/Down and Reset Settings Hardware Reset Power-Down Sequence Requirements88F6281 May reset all settings to the factory default values Reset Out SignalPower On Reset POR SYSRSTn Duration Counter Pins Sample Configuration PCI Express ResetSheeva CPU TAP Controller Reset PCI Express Root Complex Reset Reset Configuration Pin Configuration FunctionThan the third Tclk cycle after SYSRSTn de-assertion MPP33 Cpuclk to DDR CLK Ratio 0x0-0x3 = Reserved0x4 = = Disable Sscg Disable= Enable PCI Express Clock 100 MHz Differential Clock Configuration Serial ROM Initialization 88F6281 Hardware Specifications Reset ConfigurationPin Configuration Function MPP18 Reserved Serial ROM Data Structure Boot Sequence Serial ROM Initialization Operation 88F6281 Hardware Specifications Instruction Register Jtag InterfaceTAP Controller Jtag Interface ID Register Bypass RegisterJtag Scan Chain Idcode Register Map Absolute Maximum Ratings Electrical Specifications PreliminaryElectrical Specifications Preliminary Absolute Maximum Ratings 125 Storage temperature 88F6281 Hardware Specifications Absolute Maximum Ratings125 Case temperature RTC interface Parameter Min Typ Max Units Comments Recommended Operating ConditionsRecommended Operating Conditions MPP, TWSI, JTAG, SDIO, I 2S, SPI 105 Junction Temperature Analog supply for RTC in BatteryBack-up mode Internal clock inverter for crystal Thermal Power Dissipation Thermal Power Dissipation Current Consumption Interface Symbol Test Conditions Max UnitsCurrent Consumption CPU @ 1000 MHz Electrical Specifications DC Electrical SpecificationsGeneral 3.3V Cmos DC Electrical Specifications General 3.3V Interface Cmos DC Electrical Specifications VIH Rgmii 1.8V Interface Cmos DC Electrical Specifications35*VDDIO Input high level 65*VDDIO Sdram DDR2 Interface DC Electrical Specifications Sdram DDR2 Interface DC Electrical SpecificationsRTT Following table, Vddio means the Vddo power rail Twsi Interface 3.3V DC Electrical SpecificationsSPI Interface 3.3V DC Electrical Specifications Following table Vddio means the Vddo power rail TDM Interface 3.3V DC Electrical Specifications AC Electrical Specifications Reference Clock AC Timing SpecificationsReference Clock AC Timing Specifications Twsi Master Mode Reference Clock Description Symbol Min Max Units Tdmspi Output ClockSMI Master Mode Reference Clock Tclk Sdram DDR2 Interface AC Timing Table MHz @ Description Symbol Min MaxSdram DDR2 Interface AC Timing Sdram DDR2 Interface AC Timing Table MHz @ Description Symbol Min Max Units Sdram DDR2 Interface Address Timing Table Sdram DDR2 Clock Specifications Sdram DDR2 Clock SpecificationsDescription Symbol Min Max Units VTT Sdram DDR2 Interface AC Timing DiagramsSdram DDR2 Interface Test Circuit CLK Address ControlDQSn TDSI tDHI Rgmii 10/100/1000 AC Timing Table at Reduced Gigabit Media Independent Interface Rgmii AC TimingRgmii AC Timing Table Rgmii 10/100 AC Timing Table at Rgmii AC Timing Diagram Rgmii Test Circuit Gmii AC Timing Table 125 MHz Description Symbol Min MaxGigabit Media Independent Interface Gmii AC Timing Gmii Test Circuit VILmax Gmii AC Timing DiagramsTSETUP Hold TLOW THIGH 5.3 MII/MMII MAC Mode AC Timing Diagrams 5.1 MII/MMII MAC Mode AC Timing Table5.2 MII/MMII MAC Mode Test Circuit MII/MMII MAC Mode AC Timing Table MII/MMII MAC Mode Input AC Timing Diagram SMI Master Mode AC Timing Table SMI Master Mode AC Timing TableSMI Master Mode Test Circuit Serial Management Interface SMI AC Timing SMI Master Mode AC Timing Diagrams MDC Jtag Interface AC Timing Table 30 MHz Description Symbol Min Max UnitsJtag Interface AC Timing Jtag Interface Test Circuit Jtag Interface AC Timing Diagrams Jtag Interface Output Delay AC Timing Diagram Twsi AC Timing Table Two-Wire Serial Interface Twsi AC Timing100 kHz Description Symbol Twsi Master AC Timing Table Twsi AC Timing Diagrams Twsi Test Circuit Sony/Philips Digital Interconnect Format S/PDIF AC Timing 9.1 S/PDIF AC Timing TablePdif AC Timing Table 9.2 S/PDIF Test Circuit Pdif Test Circuit Inter-IC Sound I2S Test Circuit Inter-IC Sound Interface I2S AC TimingInter-IC Sound I2S AC Timing Table Inter-IC Sound I2S AC Timing Table Inter-IC Sound I2S AC Timing Diagrams Inter-IC Sound I2S Output Delay AC Timing Diagram TDM Interface AC Timing Table 192 MHz Description Symbol Min Max UnitsTime Division Multiplexing TDM Interface AC Timing TDM Interface Test Circuit TDM Interface Timing Diagrams Pclk DTXPclk DRX SPI Master Mode AC Timing Table SPI Master Mode AC Timing TableSPI Master Mode Test Circuit Description Symbol Min Max Sclk SPI Master Mode Timing DiagramsTCH tCL Data Out TDOVmin TDOVmax TCSB TCSA Secure Digital Input/Output Sdio AC Timing Table Sdio Host in High Speed Mode AC Timing TableSecure Digital Input/Output Sdio Interface AC Timing Secure Digital Input/Output Sdio Test Circuit Secure Digital Input/Output Sdio AC Timing Diagrams Sdio Host in High Speed Mode Output AC Timing Diagram Transport Stream Output Interface AC Timing Table Transport Stream TS Interface AC TimingTransport Stream Interface AC Timing Table Transport Stream Input Interface AC Timing Table Transport Stream Interface Timing Diagrams Transport Stream Interface Test Circuit Transport Stream Input Interface AC Timing Diagram Differential Interface Electrical Characteristics Differential Interface Reference Clock CharacteristicsClock frequency FCK 100.0 Symbol Min Max Units PCI Express Interface Spread Spectrum RequirementsFmod 33.0 PCI Express Interface Electrical Characteristics PCI Express Interface Driver and Receiver CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test Circuit Sata Interface Electrical Characteristics DJ5 RlodTJ5 Rlid 275.0 750.0 Differential return loss 150 MHz-300 MHz Differential return loss 600 MHz-2.4 GHzDifferential return loss 3.0 GHz-5.0 GHz 18.0 Differential return loss 300 MHz-600 MHz USB Low Speed Driver and Receiver Characteristics USB Electrical CharacteristicsUSB Driver and Receiver Characteristics Low Speed Description Sym bol Min Max Units Full Speed Description Min Max USB High Speed Driver and Receiver Characteristics High Speed Description Symbol Min MaxUSB Interface Driver Waveforms High Speed TX Eye Diagram Pattern Template Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/s Thermal Data PreliminaryThermal Data Preliminary Hsbga 288-pin Package and Dimensions Package Package Package Hsbga 288-pin Package DimensionsSymbol Common Dimension Millimeters Hsbga 88F6281 -xx-BIA2Cxxx-xxxx Part Order Numbering/Package MarkingPart Order Numbering 88F6281 Part Order Options Package Marking Part Order Numbering/Package Marking Revision History Revision Date Comments , Power Pin Assignments, on Revision History Revised , Reference Clock AC Timing Specifications, on January 28 Initial release , Current Consumption, on page 80 added the following This page is Intentionally Left Blank Page Marvell. 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Marvel Group 88F6281 Secure Digital Input/Output Sdio Interface, Sdclk Cmos Vddo, Sdcmd Cmos Vddo

Models: 88F6281

88F6281

1.2.17Secure Digital Input/Output (SDIO) Interface

Pin Name

SD_CLK

CMOS

VDDO

SD_CMD

CMOS

VDDO

CMOS

vice versa.