Marvel Group 88F6281 specifications Bit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHz

88F6281

Hardware Specifications

„I2S-specific features

•Sample rates of 44.1/48/96 kHz

•I2S input and I2S output operate at the same sample rate

•16/24-bit depths

•I2S in and I2S out support independent bit depths (16 bit/24 bit)

•Supports plain I2S, right-justified and left-justified formats

„SD/SDIO/MMC host interface

•1-bit/4-bit SDmem, SDIO, and MMC cards

•Up to 50 MHz

•Hardware generate/check CRC, on all command and data transactions on the card bus

„TDM SLIC/SLAC Codec interface

•Generic interface to standard SLIC/SLAC codec devices

•Compatible with standard PCM highway formats

•TDM protocol support for two channels, up to 128 time slots

•Dedicated SPI interface for codec management

•Integrated DMA to transfer voice data to/from memory buffer

„Two XOR engines and DMA

•Two XOR/DMA channels per XOR engine (for a total of four XOR/DMA channels)

•Chaining via linked-lists of descriptors

•Moves data from source interface to destination interface

•Supports increment or hold on both Source and Destination Addresses

•Supports XOR operation, on up to eight source blocks—useful for RAID applications

•Supports iSCSI CRC-32 calculation

„NAND flash controller

•8-bit NAND flash interface

•Glueless interface to CE Care and CE Don’t Care NAND flash devices

•Boot support

„Serial Peripheral Interface (SPI) controller

•Up to 50 MHz clock

•Supports direct boot from external SPI serial flash memory

„MPEG Transport Stream (TS) interface

•ISO/IEC 13818-1 standard compliant

•Supports any one of the following modes:

-Parallel (8 bit) input

-Parallel output

-Two independent serial interfaces

•Data rate up to 80 Mbps

„Two UART Interfaces

•16550 UART compatible

•Two pins for transmit and receive operations

•Two pins for modem control functions

„Two-Wire Serial Interface (TWSI)

•General purpose TWSI master/slave port

•Can also be used for serial ROM initialization

„50 dedicated Multi-Purpose Pins (MPPs) for peripheral functions and general purpose I/O

•Each pin can be configured independently.

•GPIO inputs can be used to register interrupts from external devices, and to generate maskable interrupts.

•Only two of the following multiplexed interfaces may be configured simultaneously:

-Audio

-TS

-TDM

-GbE Port 0 in GMII mode or GbE Port 1

„Interrupt Controller

Maskable interrupts to CPU core

(and PCI Express for a PCI Express endpoint)

„Two general purpose 32-bit timers/counters

„Internal architecture

•Mbus-L bus for high-performance, low-latency CPU core to DDR SDRAM connectivity

•Advanced Mbus architecture

•Dual port DDR SDRAM controller connectivity to both CPU and Mbus

„Bootable from

•SPI flash

•SATA device

•NAND flash

•PCI Express

•UART (for debug purpose)

„288-pin HSBGA package, 19 x 19 mm, 1 mm ball pitch

Doc. No. MV-S104859-U0 Rev. E		Copyright © 2008 Marvell
Page 6	Document Classification: Proprietary Information	December 2, 2008, Preliminary