Features

Priority queuing on receive based on Destination Address (DA), VLAN Tag, and IP TOS

Layer 2/3/4 frame encapsulation detection

TCP/IP checksum on receive and transmit

Supports proprietary 200 Mbps Marvell MII (MMII) interface

Supports four modes:

-Port 0 RGMII, Port 1 RGMII

-Port 0 RGMII, Port 1 MII/MMII

-Port 0 MII/MMII, port 1 RGMII

-Port 0 GMII, Port 1 N/A

DA filtering

„Precise Timing Protocol (PTP)

Supports precise time stamping for packets, as defined in IEEE 1588 PTP v1 and v2 and IEEE 802.1AS draft standards

Supports Flexible Time Application interface to distribute PTP clock and time to other devices in the system

Optionally accepts an external clock input for time stamping

„Audio Video Bridging networks

Supports IEEE 802.1Qav draft Audio Video Bridging networks

Supports time- and priority-aware egress pacing algorithm to prevent bunching and bursting effects—suitable for audio/video applications

Supports Egress Jitter Pacer for AVB-Class A and AVB-Class B traffic and strict priority for legacy traffic queues

„USB 2.0 port

Serves as a peripheral or host

USB 2.0 compliant

Integrated USB 2.0 PHY

Enhanced Host Controller Interface (EHCI) compatible as a host

As a host, supports direct connection to all peripheral types (LS, FS, HS)

As a peripheral, connects to all host types (HS, FS) and hubs

Up to four independent endpoints, supporting control, interrupt, bulk, and isochronous data transfers

Dedicated DMA for data movement between memory and port

„Two Integrated Marvell 3 Gbps (Gen2i) SATA PHYs

Compliant with SATA II Phase 1 specifications

-Supports SATA II Native Command Queuing (NCQ), up to 128 outstanding commands per port

-Fully supports first party DMA (FPDMA)

-Backwards compatible with SATA I devices

Supports SATA II Phase 2 advanced features

-3 Gbps (Gen2i) SATA II speed

-Port Multiplier (PM)—Performs FIS-based switching, as defined in SATA working group PM definition

-Port Selector (PS)—Issues the protocol-based Out-Of-Band (OOB) sequence for selecting the active host port

Supports device 48-bit addressing

Supports ATA Tag Command Queuing

„SATA II Host Controller

Enhanced-DMA (EDMA) for the SATA ports

Automatic command execution, without host intervention

Command queuing support, for up to 32 outstanding commands

Separate SATA request/response queues

64-bit addressing support for descriptors and data buffers in system memory

Read ahead

Advanced interrupt coalescing

Target mode operation—supports attaching two 88F6281 controllers through their Serial-ATA ports, enabling data communication between the 88F6281 controllers

Advanced drive diagnostics via the ATA SMART command

„Cryptographic engine

Hardware implementation on encryption and authentication engines, to boost packet processing speed

Dedicated DMA to feed the hardware engines with data from the internal SRAM memory or from the DDR memory

Implements AES, DES, and 3DES encryption algorithms

Implements SHA1 and MD5 authentication algorithms

„S/PDIF / I2S Audio In/Out interface

Either S/PDIF or I2S inputs can be active at one time

Both S/PDIF and I2S outputs can be simultaneously active, transferring the same PCM data

„S/PDIF-specific features

Compliant with 60958-1, 60958-3, and IEC61937 specifications

Sample rates of 44.1/48/96 kHz

16/20/24-bit depths

Copyright © 2008 Marvell

 

Doc. No. MV-S104859-U0 Rev. E

December 2, 2008, Preliminary

Document Classification: Proprietary Information

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Marvel Group 88F6281 specifications Features, Supports Ieee 802.1Qav draft Audio Video Bridging networks