Marvel Group 88F6281 8.6 AC Electrical Specifications

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 86 Document Classification: Proprietary Information December 2, 2008, Preliminary
8.6 AC Electrical Specifications
See Section8.7, Differential Interface Electrical Characteristics, on page118 for differential interface
specifications.
8.6.1 Reference Clock AC Timing Specifications
Table 45: Reference Clock AC Timing Specifications
Description Symbol Min Max Units Notes
CPU and Core Reference Clock
Frequency FREF_CLK_XIN 25 -
50ppm 25 + 50ppm MHz
Clock duty cycle DCREF_CLK_XIN 40 60 %
Slew rate SRREF_CLK_XIN 0.7 V/ns 1
Pk-Pk jitter JRREF_CLK_XIN 200 ps
Ethernet Reference Clock
Frequency in MII/MMII-MAC mode FGE_TXCLK_OUT 2.5 -
100ppm 50 + 100ppm MHz 7
FGE_RXCLK
MII/MMII-MAC mode clock duty cycle DCGE_TXCLK_OUT 35 65 % 7
DCGE_RXCLK
Slew rate SRGE_TXCLK_OUT 0.7 V/ns 1, 7
SRGE_RXCLK
Audio External Reference Clock
Audio external reference clock FAU_EXTCLK 256 X FskHz 3
S/PDIF Recovered Master Clock
S/PDIF recovered master clock FAU_SPDFRMCLK 256 X FskHz 3
I2S Reference Clock
I2S clock FI2S_BCLK 64 X FskHz 3
SPI Output Clock
SPI output clock FSPI_SCK TCLK/30 TCLK/4 MHz 2
RTC Reference Clock
RTC_XIN crystal frequency FRTC_XIN 32.768 kHz 4
Transport Stream (TS) Output Mode Reference Clock
TS output clock in parallel mode FTS0_CLK, FTS1_CLK 9.61 12.5 MHz 5
TS output clock in serial mode FTS0_CLK, FTS1_CLK 9.61 83 MHz 5
Transport Stream Input Mode Reference Clock
TS input clock in parallel mode FTS0_CLK, FTS1_CLK 13.5 MHz
TS input clock in serial mode FTS0_CLK, FTS1_CLK 83 MHz
Transport Stream External Reference Clock
TS external clock in parallel mode FEXT_CLK 9.61 12.5 MHz 5
TS external clock in serial mode FEXT_CLK 9.61 83 MHz 5