Marvel Group 88F6281 specifications PCI Express Reset, Sheeva CPU TAP Controller Reset

88F6281

Hardware Specifications

6.3PCI Express Reset

6.3.1PCI Express Root Complex Reset

As a Root Complex, the device may generate a Hot Reset to the PCI Express port. Upon CPU setting the PCI Express Control register’s <conf_mstr_hot_reset> bit, the PCI Express unit sends a Hot Reset indication to the Endpoint, see the PCI Express Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

6.3.2PCI Express Endpoint Reset

When a Hot Reset packet is received:

„A maskable interrupt is asserted.

„If the <conf_dis_hot_rst_reg_rst> field in the PCI Express Debug Control register is cleared, the device also resets the PCI Express register file to its default values.

„The device triggers an internal reset, if not masked by the <conf_msk_hot_reset> field in the PCI Express Debug Control register.

Link failure is detected if the PCI Express link was up (LTTSSM L0 state) and dropped back to an inactive state (LTSSM Detect state). When Link failure is detected:

„A maskable interrupt is asserted.

„If the <conf_dis_link_fail_reg_rst> field in the PCI Express Debug Control register is cleared, the device also resets the PCI Express register file to its default values.

„The device triggers an internal reset, if the <conf_msk_link_fail> field is not masked by PCI Express Debug Control register.

Both link fail and hot reset conditions trigger a chip internal reset (if not masked in the PCI Express interface). All the chip logic is reset to the default values, except for sticky registers and the sample on reset logic. In addition, these events can trigger reset to the board, using one of the following:

„PEX_RST_OUTn signal (multiplexed on MPP).

„SYSRST_OUTn output (multiplexed on MPP)—if not masked by the <PexRstOutEn> bit.

The external reset logic (on the board) may assert the SYSRSTn input pin and reset the entire chip.

6.4Sheeva™ CPU TAP Controller Reset

The Sheeva™ CPU Test Access Port (TAP) controller is reset when JT_RSTn is set and

JT_TMS_CPU is active.

6.5Pins Sample Configuration

The following pins are sampled during SYSRSTn de-assertion:

„Internal pull up/down resistors set the default mode (see Section 1.3, Internal Pull-up and Pull-down Pins, on page 48).

„Higher value, external pull up/down resistors are required to change the default mode of operation.

These signals must remain pulled up or down until SYSRSTn de-assertion (zero hold time in respect to SYSRSTn de-assertion).

Doc. No. MV-S104859-U0 Rev. E		Copyright © 2008 Marvell
Page 66	Document Classification: Proprietary Information	December 2, 2008, Preliminary