Preface

About this Document
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 15
Preface

About this Document

This datasheet provides the hardware specifications for the 88F6281 integrated controller. The
hardware specifications include detailed pin information, configuration settings, electrical
characteristics and physical specifications.
This datasheet is intended to be the basic source of information for designers of new systems.
In this document, the “88F6281” is often referred to as the “device”.

Related Documentation

The following documents contain additional information related to the 88F6281:
88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications,
Doc No. MV-S104860-U0
Sheeva™ 88SV131 ARM v5TE Processor Core with MMU and L1/L2 Cache Datasheet,
Doc No. MV-S104950-U0
Unified Layer 2 (L2) Cache for Sheeva™ CPU Cores Addendum, Doc No. MV-S104858-U0
88F6180, 88F6190, 88F6192, and 88F6281 Functional Errata, Interface Guidelines, and
Restrictions, Doc No. MV-S501157-U0
88F6180, 88F6190, 88F6192, and 88F6281 Design Guide, Doc No. MV-S301398-001
AN-63: Thermal Management for Marvell Technology Products Doc No. MV-S300281-001
AN-179: TWSI Software Guidelines for Discovery™, Horizon™, and Feroceon® Devices,
Doc No. MV-S300754-001
AN-183: 88F5181 and 88F5281 Big Endian and Little Endian Support,
Doc No. MV-S300767-001
AN-249: Configuring the Marvell® SATA PHY to Transmit Predefined Test Patterns,
Doc No. MV-S301342-001
AN-260 System Power-Saving Methods for 88F6180, 88F6190, 88F6192, and 88F6281,
Doc No. MV-S301454-001
TB-227: Differences Between the 88F6190, 88F6192, and 88F6281 Stepping Z0 and A0,
Doc No. MV-S105223-001
White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Doc No. MV-S700019-00
ARM Architecture Reference Manual, Second Edition
PCI Express Base Specification, Revision 1.1
Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel,
Lucent, Microsoft, NEC, Philips
Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95,
November 2000, Intel Corporation
ARC USB-HS OTG High-Speed Controller Core reference V 4.0.1
Federal Information Processing Standards (FIPS) 46-2 (Data Encryption Standard)
FIPS 81 (DES Modes of Operation)
FIPS 180-1 (Secure Hash Standard)
FIPS draft - Advanced Encryption Standard (Rijndeal)
1. This document is a Marvell proprietary, confidential document, requiring an NDA and can be downloaded from the
Marvell Extranet.