System Power Up/Down and Reset Settings | Marvel Group 88F6281

System Power Up/Down and Reset Settings

Power-Up/Down Sequence Requirements

6 System Power Up/Down and Reset Settings

This section provides information about the device power-up/down sequence and configuration at reset.

6.1Power-Up/Down Sequence Requirements

6.1.1Power-Up Sequence Requirements

These guidelines must be applied to meet the 88F6281 device power-up requirements:

The non-core voltages (I/O and Analog) as listed in Table 31 must reach 70% of their voltage level before the core voltages reach 70% of their voltage level.

The order of the power-up sequence between the non-core voltages is unimportant so long as the non-core voltages power up before the core voltages reach 70% of their voltage level (shown in Figure 2).

The order of the power-up sequence between the core voltages (VDD and VDD_CPU) is unimportant.

The reset signal(s) must be asserted before the core voltages reach 70% of their voltage level (shown in Figure 2).

The reference clock(s) inputs must toggle with their respective voltage levels before the core voltages reach 70% of their voltage level (shown in Figure 2).

If VHV is set to burning mode (2.5V), which is a higher voltage than the VDD voltage, VDD must be powered before VHV, to prevent the fuse from being accidentally burned.

Table 31: I/O and Core Voltages

	Non-Core Voltages		Core Voltages

I/O Voltages		Analog Power Supplies

VDD_GE_A		CPU_PLL_AVDD	VDD
VDD_GE_B		CORE_PLL_AVDD	VDD_CPU
VDD_M		PEX_AVDD
VDDO		RTC_AVDD
		SATA0_AVDD
		SATA1_AVDD
		SSCG_AVDD
		XTAL_AVDD
		USB_AVDD

Copyright © 2008 Marvell		Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary	Document Classification: Proprietary Information	Page 63

Image 63

Marvel Group 88F6281 System Power Up/Down and Reset Settings, Power-Up/Down Sequence Requirements, O and Core Voltages

Contents

88F6281 Hardware Specifications 88F6281 Hardware Specifications Document Conventions Document StatusDoc Status Preliminary Technical Publication Hardware Specifications 88F6281Integrated Controller High-performance CPU core, running at up to Features Supports Ieee 802.1Qav draft Audio Video Bridging networks Features Bit/4-bit SDmem, SDIO, and MMC cards Up to 50 MHz GbE Port 0 in Gmii mode or GbE Port TDM X16 Table of Contents 132 Table of Contents129 130 Clocking List of Tables List of Tables Hsbga 288-pin Package Dimensions 131 88F6281 Part Order Options 132Revision History 134 List of Figures Pin and Signal Descriptions Inter-IC Sound I2S Test Circuit 107 About this Document Related DocumentationPreface Following conventions are used in this document Document Conventions Pin and Signal Descriptions Misc PCI Express PowerPin Logic Flash Term Definition Pin DescriptionsPin Functions and Assignments Table Key Interface Pin Prefix Codes SPI Sdio TDM PTP 88F6281 Hardware Specifications Interface Pin Prefix CodesRTC MPP Twsi Uart Power Supply Pins Power Pin AssignmentsPin Name Description Type 88F6281 Hardware Specifications Power Pin Assignments Pin Name Power Description Type Rail Miscellaneous Pin AssignmentMiscellaneous Pin Assignments Mcke Sstl Vddm DDR Sdram Interface Pin AssignmentsDDR Sdram Interface Pin Assignments Mclkout Sstl Vddm Mncal Mstartburst Sstl VddmMstart Sstl Vddm Burstin Mpcal PCI Express Interface Pin Assignments PCI Express Interface Pin Assignments Pin Name Power Rail Description Type Sata Interface Pin AssignmentsSata Port Interface Pin Assignment Pin Name Type Power Rail Description Gigabit Ethernet Port Interface Pin AssignmentsGigabit Ethernet Port0/1 Interface Pin Assignments Gerxctl Cmos Vddgea Gerxclk Cmos VddgeaCmos Vddgeb To any clock Gmii Receive ErrorMPP2724 MII/MMII Collision Detect MPP32/GE112 MII/MMII Transmit ErrorGmii Transmit Error MII/MMII Receive Error Gemdio Cmos Vddgea Serial Management Interface SMI Interface Pin AssignmentsSerial Management Interface SMI Pin Assignments Gemdc Cmos Vddgea USB 2.0 Interface Pin Assignments USB 2.0 Interface Pin AssignmentsUSB 2.0 Data Differential Pair Jtag Pin Assignment Jtag Interface Pin Assignment Rtcxout Real Time Clock RTC Interface Pin AssignmentsRTC Interface Pin Assignments Rtcxin Nfale Cmos Vddo Nand Flash Interface Pin AssignmentNand Flash Interface Pin Assignment Nfcle Cmos Vddo MPP Interface Pin Assignment MPP Interface Pin Assignment Twsck Cmos Vddo Two-Wire Serial Interface Twsi InterfaceTwo-Wire Serial Interface Twsi Interface Pin Assignment Twsda Cmos Vddo Uart Port 0/1 Interface Pin Assignment Uart Interface Fs is the audio sample rate Audio S/PDIF / I2S Interface Signal AssignmentAudio S/PDIF / I2S Interface Multiplexing option SPICSn Serial Peripheral Interface SPI Interface Signal AssignmentPin Name Pin Type Power Rail Description Serial Peripheral Interface SPI Interface Secure Digital Input/Output Sdio Interface Sdclk Cmos VddoSdcmd Cmos Vddo Time Division Multiplexing TDM Interface Time Division Multiplexing TDM Interface Signal Assignment Tdmspimiso Cmos Vddo Tdmspimosi Cmos Vddo Transport Stream TS Interface Transport Stream TS Interface Signal Assignment Cmos Vddo TS0DATA6 Vddgeb TSMP7 Cmos VddoTSMP8 Cmos Vddo TSMP9 Cmos Vddo Ptpeventreq Cmos Vddo Precise Timing Protocol PTP Interface Signal AssignmentPrecise Timing Protocol PTP Interface Ptpclk Cmos Vddo Internal Pull-up and Pull-down Pins Internal Pull-up and Pull-down PinsPin Name Pin Number Pull up/Pull down Unused Interface Strapping Unused Interface StrappingUnused Interface Strapping 88F6281 pin list is provided as an Excel file attachment 88F6281 Pin Map and Pin List Multi-Purpose Pins Functional Summary Pin MultiplexingPin Multiplexing Sata LEDs Audio Nand flash GbE MPP FunctionalityMPP190 MPP3520 MPP4936 Gpio Sysrsto Spimosi MPP Function Summary MPP Function Summary TSMP0 Tdmspi Auspdifi Configuration, on Ethernet Ports Pins Multiplexing Gigabit Ethernet GbE Pins Multiplexing on MPP MPP34 MII1TXEN out GE114 MPP35 MII1RXERR GE115 TS Port Pin Multiplexing Tsmp TS Multiplexing Pins on MPP Clock Type Description Clocking88F6281Clocks Lists the clocks in the 88F6281 Ptpclk Clocking 88F6281ClocksSupported Clock Combinations Sata PHY PLL Spread Spectrum Clock Generator Sscg 88F6192, and 88F6281 Functional Specifications System Power Up/Down and Reset Settings System Power Up/Down and Reset SettingsPower-Up/Down Sequence Requirements Power-Up Sequence Requirements Hardware Reset Power-Down Sequence Requirements88F6281 SYSRSTn Duration Counter Reset Out SignalPower On Reset POR May reset all settings to the factory default values PCI Express Root Complex Reset PCI Express ResetSheeva CPU TAP Controller Reset Pins Sample Configuration Reset Configuration Pin Configuration FunctionThan the third Tclk cycle after SYSRSTn de-assertion MPP33 Cpuclk to DDR CLK Ratio 0x0-0x3 = Reserved0x4 = PCI Express Clock 100 MHz Differential Clock Configuration Sscg Disable= Enable = Disable Serial ROM Data Structure 88F6281 Hardware Specifications Reset ConfigurationPin Configuration Function MPP18 Reserved Serial ROM Initialization Serial ROM Initialization Operation Boot Sequence 88F6281 Hardware Specifications Jtag Interface Jtag InterfaceTAP Controller Instruction Register Idcode Register Map Bypass RegisterJtag Scan Chain ID Register Absolute Maximum Ratings Electrical Specifications PreliminaryElectrical Specifications Preliminary Absolute Maximum Ratings RTC interface 88F6281 Hardware Specifications Absolute Maximum Ratings125 Case temperature 125 Storage temperature MPP, TWSI, JTAG, SDIO, I 2S, SPI Recommended Operating ConditionsRecommended Operating Conditions Parameter Min Typ Max Units Comments Internal clock inverter for crystal Analog supply for RTC in BatteryBack-up mode 105 Junction Temperature Thermal Power Dissipation Thermal Power Dissipation CPU @ 1000 MHz Interface Symbol Test Conditions Max UnitsCurrent Consumption Current Consumption General 3.3V Interface Cmos DC Electrical Specifications DC Electrical SpecificationsGeneral 3.3V Cmos DC Electrical Specifications Electrical Specifications 65*VDDIO Rgmii 1.8V Interface Cmos DC Electrical Specifications35*VDDIO Input high level VIH Sdram DDR2 Interface DC Electrical Specifications Sdram DDR2 Interface DC Electrical SpecificationsRTT Following table Vddio means the Vddo power rail Twsi Interface 3.3V DC Electrical SpecificationsSPI Interface 3.3V DC Electrical Specifications Following table, Vddio means the Vddo power rail TDM Interface 3.3V DC Electrical Specifications AC Electrical Specifications Reference Clock AC Timing SpecificationsReference Clock AC Timing Specifications Tclk Description Symbol Min Max Units Tdmspi Output ClockSMI Master Mode Reference Clock Twsi Master Mode Reference Clock Sdram DDR2 Interface AC Timing Table MHz @ Description Symbol Min MaxSdram DDR2 Interface AC Timing Sdram DDR2 Interface AC Timing Table Sdram DDR2 Interface Address Timing Table MHz @ Description Symbol Min Max Units Sdram DDR2 Clock Specifications Sdram DDR2 Clock SpecificationsDescription Symbol Min Max Units CLK Sdram DDR2 Interface AC Timing DiagramsSdram DDR2 Interface Test Circuit VTT Address ControlDQSn TDSI tDHI Rgmii 10/100 AC Timing Table at Reduced Gigabit Media Independent Interface Rgmii AC TimingRgmii AC Timing Table Rgmii 10/100/1000 AC Timing Table at Rgmii Test Circuit Rgmii AC Timing Diagram Gmii Test Circuit 125 MHz Description Symbol Min MaxGigabit Media Independent Interface Gmii AC Timing Gmii AC Timing Table TLOW THIGH Gmii AC Timing DiagramsTSETUP Hold VILmax MII/MMII MAC Mode AC Timing Table 5.1 MII/MMII MAC Mode AC Timing Table5.2 MII/MMII MAC Mode Test Circuit 5.3 MII/MMII MAC Mode AC Timing Diagrams MII/MMII MAC Mode Input AC Timing Diagram Serial Management Interface SMI AC Timing SMI Master Mode AC Timing TableSMI Master Mode Test Circuit SMI Master Mode AC Timing Table MDC SMI Master Mode AC Timing Diagrams Jtag Interface Test Circuit 30 MHz Description Symbol Min Max UnitsJtag Interface AC Timing Jtag Interface AC Timing Table Jtag Interface Output Delay AC Timing Diagram Jtag Interface AC Timing Diagrams Twsi Master AC Timing Table Two-Wire Serial Interface Twsi AC Timing100 kHz Description Symbol Twsi AC Timing Table Twsi Test Circuit Twsi AC Timing Diagrams Sony/Philips Digital Interconnect Format S/PDIF AC Timing 9.1 S/PDIF AC Timing TablePdif AC Timing Table Pdif Test Circuit 9.2 S/PDIF Test Circuit Inter-IC Sound I2S AC Timing Table Inter-IC Sound Interface I2S AC TimingInter-IC Sound I2S AC Timing Table Inter-IC Sound I2S Test Circuit Inter-IC Sound I2S Output Delay AC Timing Diagram Inter-IC Sound I2S AC Timing Diagrams TDM Interface Test Circuit 192 MHz Description Symbol Min Max UnitsTime Division Multiplexing TDM Interface AC Timing TDM Interface AC Timing Table TDM Interface Timing Diagrams Pclk DTXPclk DRX Description Symbol Min Max SPI Master Mode AC Timing TableSPI Master Mode Test Circuit SPI Master Mode AC Timing Table Data Out TDOVmin TDOVmax TCSB TCSA SPI Master Mode Timing DiagramsTCH tCL Sclk Secure Digital Input/Output Sdio Test Circuit Sdio Host in High Speed Mode AC Timing TableSecure Digital Input/Output Sdio Interface AC Timing Secure Digital Input/Output Sdio AC Timing Table Sdio Host in High Speed Mode Output AC Timing Diagram Secure Digital Input/Output Sdio AC Timing Diagrams Transport Stream Input Interface AC Timing Table Transport Stream TS Interface AC TimingTransport Stream Interface AC Timing Table Transport Stream Output Interface AC Timing Table Transport Stream Interface Test Circuit Transport Stream Interface Timing Diagrams Transport Stream Input Interface AC Timing Diagram Differential Interface Electrical Characteristics Differential Interface Reference Clock CharacteristicsClock frequency FCK 100.0 Symbol Min Max Units PCI Express Interface Spread Spectrum RequirementsFmod 33.0 PCI Express Interface Electrical Characteristics PCI Express Interface Driver and Receiver CharacteristicsPCI Express Interface Driver and Receiver Characteristics PCI Express Interface Test Circuit PCI Express Interface Test Circuit Sata Interface Electrical Characteristics Rlid RlodTJ5 DJ5 18.0 Differential return loss 300 MHz-600 MHz Differential return loss 600 MHz-2.4 GHzDifferential return loss 3.0 GHz-5.0 GHz 275.0 750.0 Differential return loss 150 MHz-300 MHz Low Speed Description Sym bol Min Max Units USB Electrical CharacteristicsUSB Driver and Receiver Characteristics USB Low Speed Driver and Receiver Characteristics Min Max Full Speed Description USB High Speed Driver and Receiver Characteristics High Speed Description Symbol Min MaxUSB Interface Driver Waveforms High Speed TX Eye Diagram Pattern Template Symbol Definition Airflow Value C/W 0m/s 1m/s 2m/s Thermal Data PreliminaryThermal Data Preliminary Package Hsbga 288-pin Package and Dimensions Hsbga Package Hsbga 288-pin Package DimensionsSymbol Common Dimension Millimeters Package 88F6281 Part Order Options Part Order Numbering/Package MarkingPart Order Numbering 88F6281 -xx-BIA2Cxxx-xxxx Part Order Numbering/Package Marking Package Marking Revision Date Comments Revision History Revision History , Power Pin Assignments, on Revised , Reference Clock AC Timing Specifications, on , Current Consumption, on page 80 added the following January 28 Initial release This page is Intentionally Left Blank Page Marvell. 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