Pin Multiplexing

Gigabit Ethernet (GbE) Pins Multiplexing on MPP

4.2Gigabit Ethernet (GbE) Pins Multiplexing on MPP

The 88F6281 has 14 dedicated pins for its GbE port. (12 RGMII pins, an MDC pin, and an MDIO pin).

For the 88F6281, additional GbE interface pins are multiplexed on the MPPs, to serve as the following interfaces to an external PHY or switch.

„Two RGMII ports

„One RGMII port and one MMII/MII port

(either port 0 as RGMII and port 1 as MMII/MII or port 0 as MMII/MII and port 1 as RGMII)

„One GMII port (port 0)

Table 27 summarizes the GbE port pins multiplexing.

Table 27: Ethernet Ports Pins Multiplexing

Pin Name

1xGMII

RGMII0+MII1/

2xRGMII

MII0/MMII0+

 

 

MMII1

 

RGMII1

GE_TXCLKOUT

GMII0_TXCLKOUT

RGMII0_TXCLKOUT

RGMII0_TXCLKOUT

MII0_TXCLK (in)

 

(out)

(out)

(out)

 

GE_TXD[3:0]

GMII0_TXD[3:0] (out)

RGMII0_TXD[3:0]

RGMII0_TXD[3:0]

MII0_TXD[3:0] (out)

 

 

(out)

(out)

 

GE_TXCTL

GMII0_TXEN (out)

RGMII0_TXCTL (out)

RGMII0_TXCTL (out)

MII0_TXEN (out)

GE_RXD[3:0]

GMII0_RXD[3:0] (in)

RGMII0_RXD[3:0] (in)

RGMII0_RXD[3:0] (in)

MII0_RXD[3:0] (in)

GE_RXCTL

GMII0_RXDV (in)

RGMII0_RXCTL (in)

RGMII0_RXCTL (in)

MII0_RXDV (in)

GE_RXCLK

GMII0_RXCLK (in)

RGMII0_RXCLK (in)

RGMII0_RXCLK (in)

MII0_RXCLK (in)

MPP[8] or

NA

NA

NA

MII0_RXERR (in)

MPP[35]

 

 

 

 

MPP[8] or

NA

NA

NA

MII0_COL (in)

MPP[14]

 

 

 

 

MPP[9] or

NA

NA

NA

MII0_CRS (in)

MPP[16]

 

 

 

 

MPP [23:20] /

GMII0_TXD[7:4] (out)

MII1_TXD[3:0] (out)

RGMII1_TXD[3:0]

RGMII1_TXD[3:0]

GE1[3:0]

 

 

(out)

(out)

MPP_[27:24] /

GMII0_RXD[7:4] (in)

MII1_RXD[3:0] (in)

RGMII1_RXD[3:0] (in)

RGMII1_RXD[3:0] (in)

GE1[7:4]

 

 

 

 

MPP_28 /

GMII0_COL (in)

MII1_COL (in)

NA

NA

GE1[8]

 

 

 

 

MPP_29 /

GMII0_TXCLK (in)

MII1_TXCLK (in)

NA

NA

GE1[9]

 

 

 

 

MPP_30 /

GMII0_RXERR (in)

MII1_RXDV (in)

RGMII1_RXCTL (in)

RGMII1_RXCTL (in)

GE1[10]

 

 

 

 

MPP_31 /

NA

MII1_RXCLK (in)

RGMII1_RXCLK (in)

RGMII1_RXCLK (in)

GE1[11]

 

 

 

 

MPP_32 /

GMII0_CRS (in)

MII1_CRS (in)

RGMII1_TXCLKOUT

RGMII1_TXCLKOUT

GE1[12]

 

 

(out)

(out)

MPP_33 /

GMII0_TXERR (out)

MII1_TXERR (out)

RGMII1_TXCTL (out)

RGMII1_TXCTL (out)

GE1[13]

 

 

 

 

 

 

 

 

 

Copyright © 2008 Marvell

 

Doc. No. MV-S104859-U0 Rev. E

December 2, 2008, Preliminary

Document Classification: Proprietary Information

Page 57

Page 57
Image 57
Marvel Group 88F6281 specifications Gigabit Ethernet GbE Pins Multiplexing on MPP, Ethernet Ports Pins Multiplexing