Cypress CY7C1410JV18, CY7C1412JV18 manual Maximum Ratings, DC Electrical Characteristics

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CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature

–65°C to +150°C

Ambient Temperature with Power Applied

.... –10°C to +85°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

.......–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage [11]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

 

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)..

> 2001V

Latch-up Current

...................................................

 

> 200 mA

Operating Range

 

 

 

 

 

 

 

 

 

Ambient

VDD [15]

VDDQ [15]

Range

 

Temperature (TA)

Commercial

 

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

VDD

Industrial

 

–40°C to +85°C

 

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range [12]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 16

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 17

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.3

V

VIL

Input LOW Voltage

 

 

 

–0.3

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

 

5

 

5

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

5

 

5

μA

VREF

Input Reference Voltage [18]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD

VDD Operating Supply

VDD = Max,

267MHz

(x8)

 

 

1330

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

1330

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

1370

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1460

 

 

 

 

 

 

 

 

 

 

 

 

 

250MHz

(x8)

 

 

1200

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

1200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

1230

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1290

 

 

 

 

 

 

 

 

 

 

ISB1

Automatic Power down

Max VDD,

267MHz

(x8)

 

 

375

mA

 

Current

Both Ports Deselected,

 

 

 

 

 

 

 

 

(x9)

 

 

375

 

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

380

 

 

 

f = fMAX = 1/tCYC,

 

 

 

 

 

 

Inputs Static

 

(x36)

 

 

385

 

 

 

 

 

 

 

 

 

 

 

 

 

250MHz

(x8)

 

 

345

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

345

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

350

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

350

 

 

 

 

 

 

 

 

 

 

Notes

15.Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

16.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

17.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

18.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

Document #: 001-12561 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideDoff Logic Block Diagram CY7C1410JV18Logic Block Diagram CY7C1425JV18 Logic Block Diagram CY7C1412JV18 Logic Block Diagram CY7C1414JV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1410JV18 4M x CY7C1425JV18 4M xCY7C1414JV18 1M x CY7C1412JV18 2M xWPS BWS Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Application Example Programmable ImpedanceEcho Clocks Sram #1Truth Table Write Cycle DescriptionsRPS WPS BWS0 BWS1BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up WaveformsPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics CapacitanceThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Cypress Consortium Description 267 MHz 250 MHz UnitParameter Min Max DLL TimingWrite NOP Switching WaveformsWrite Read Ordering Information Package Diagram Ball Fbga 15 x 17 x 1.40 mmREV ECN no Issue ORIG. Description of Change Date Document HistoryVKN VKN/AESA