Cypress CY7C1414JV18 manual Power Up Sequence in QDR-II Sram, Power Up Waveforms, DLL Constraints

CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18

Power Up Sequence in QDR-II SRAM

QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.

Power Up Sequence

■Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW)

❐Apply VDD before VDDQ

❐Apply VDDQ before VREF or at the same time as VREF

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid DLL locking provide 1024 cycles stable clock to relock to the desired clock frequency.

■Provide stable power and clock (K, K) for 1024 cycles to lock the DLL.

Power Up Waveforms

~ ~

K

K

	~ ~
Unstable Clock	> 1024 Stable clock	Start Normal
		Operation

Clock Start (Clock Starts after VDD/ V DDQ Stable)

VDD/ VDDQ VDD/ V DDQ Stable (< +/- 0.1V DC per 50ns )

Fix High (or tied to VDDQ)

DOFF

Document #: 001-12561 Rev. *D Page 19 of 26

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