Cypress CY8C24223 manual Register Map Bank 1 Table Configuration Space, Name Addr 1,Hex Access

Page 13

CY8C24123

CY8C24223, CY8C24423

Table 8. Register Map Bank 0 Table: User Space (continued)

Name

Addr (0,Hex)

Access

Name

Addr (0,Hex)

Access

Name

Addr (0,Hex)

Access

Name

Addr (0,Hex)

Access

DCB03DR2

2E

RW

 

6E

 

 

AE

 

ACC_DR3

EE

RW

 

 

 

 

 

 

 

 

 

 

 

 

DCB03CR0

2F

#

 

6F

 

 

AF

 

ACC_DR2

EF

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

ACB00CR3

70

RW

RDI0RI

B0

RW

 

F0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

ACB00CR0

71

RW

RDI0SYN

B1

RW

 

F1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

ACB00CR1

72

RW

RDI0IS

B2

RW

 

F2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

ACB00CR2

73

RW

RDI0LT0

B3

RW

 

F3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

 

ACB01CR3

74

RW

RDIOLT1

B4

RW

 

F4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

 

ACB01CR0

75

RW

RDI0RO0

B5

RW

 

F5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

 

ACB01CR1

76

RW

RDI0RO1

B6

RW

 

F6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

37

 

ACB01CR2

77

RW

 

B7

 

CPU_F

F7

RL

 

 

 

 

 

 

 

 

 

 

 

 

 

38

 

 

78

 

 

B8

 

 

F8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

 

 

79

 

 

B9

 

 

F9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3A

 

 

7A

 

 

BA

 

 

FA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3B

 

 

7B

 

 

BB

 

 

FB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3C

 

 

7C

 

 

BC

 

 

FC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3D

 

 

7D

 

 

BD

 

 

FD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3E

 

 

7E

 

 

BE

 

CPU_SCR1

FE

#

 

 

 

 

 

 

 

 

 

 

 

 

 

3F

 

 

7F

 

 

BF

 

CPU_SCR0

FF

#

 

 

 

 

 

 

 

 

 

 

 

 

Blank fields are Reserved and must not be accessed.

 

 

# Access is bit specific.

 

 

 

 

Table 9. Register Map Bank 1 Table: Configuration Space

Name

Addr (1,Hex)

Access

Name

Addr (1,Hex)

Access

Name

Addr (1,Hex)

Access

Name

Addr (1,Hex)

Access

PRT0DM0

00

RW

 

40

 

ASC10CR0

80

RW

 

C0

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT0DM1

01

RW

 

41

 

ASC10CR1

81

RW

 

C1

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT0IC0

02

RW

 

42

 

ASC10CR2

82

RW

 

C2

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT0IC1

03

RW

 

43

 

ASC10CR3

83

RW

 

C3

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT1DM0

04

RW

 

44

 

ASD11CR0

84

RW

 

C4

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT1DM1

05

RW

 

45

 

ASD11CR1

85

RW

 

C5

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT1IC0

06

RW

 

46

 

ASD11CR2

86

RW

 

C6

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT1IC1

07

RW

 

47

 

ASD11CR3

87

RW

 

C7

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT2DM0

08

RW

 

48

 

 

88

 

 

C8

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT2DM1

09

RW

 

49

 

 

89

 

 

C9

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT2IC0

0A

RW

 

4A

 

 

8A

 

 

CA

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT2IC1

0B

RW

 

4B

 

 

8B

 

 

CB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0C

 

 

4C

 

 

8C

 

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0D

 

 

4D

 

 

8D

 

 

CD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0E

 

 

4E

 

 

8E

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0F

 

 

4F

 

 

8F

 

 

CF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

50

 

ASD20CR0

90

RW

GDI_O_IN

D0

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

51

 

ASD20CR1

91

RW

GDI_E_IN

D1

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

52

 

ASD20CR2

92

RW

GDI_O_OU

D2

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

53

 

ASD20CR3

93

RW

GDI_E_OU

D3

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

54

 

ASC21CR0

94

RW

 

D4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

55

 

ASC21CR1

95

RW

 

D5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

56

 

ASC21CR2

96

RW

 

D6

 

 

 

 

 

 

 

 

 

 

 

 

 

Blank fields are Reserved and must not be accessed.

 

 

# Access is bit specific.

 

 

 

 

Document Number: 38-12011 Rev. *G

Page 13 of 43

[+] Feedback

Image 13
Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court PSoC Core PSoC Functional OverviewDigital System Analog System Analog System Block DiagramGetting Started PSoC Device CharacteristicsAdditional System Resources PSoC Designer Software Subsystems Development ToolsDevice Editor Design BrowserHardware Tools User Modules and the PSoC Development ProcessDebugger Online Help SystemDocument Conventions Pin Part Pinout PinoutsActive high external reset with internal Switch Mode Pump SMP connection toExternal components required SCLExtclk Pin Part Pinout MLF Type Description Digital Analog NameRegister Conventions Register ReferenceRegister Mapping Tables Abbreviations UsedRegister Map Bank 0 Table User Space Name Addr 0,Hex AccessName Addr 1,Hex Access Register Map Bank 1 Table Configuration SpaceCY8C24123 CY8C24223, CY8C24423 Units of Measure Symbol Unit of Measure Electrical SpecificationsAbsolute Maximum Ratings Symbol Description Min Typ Units Operating TemperatureOperating Temperature Symbol Description Min Typ Max Units Absolute Maximum RatingsDC Chip-Level Specifications DC Electrical CharacteristicsDC Gpio Specifications Symbol Description Min Typ Max Units DC General Purpose IO SpecificationsDC Operational Amplifier Specifications Psrr OA Power = Low At high power. For all Power = Medium Input Capacitance Port 0 Analog Pins Package and pinPower = High High power, high opamp Vdd Power = Low Power = Medium Power = High is 5V onlyPsrr OB DC Analog Output Buffer SpecificationsBAT5V DC Switch Mode Pump SpecificationsBAT3V PSoCTMVdd/2 + BG + DC Analog Reference SpecificationsVdd/2 BG + CT Block Power = High Agnd = P24 P24 = Vdd/2 Agnd = Vdd/2 a CT Block Power = HighBandgap Voltage Reference DC POR and LVD Specifications DC Analog PSoC Block SpecificationsDC Programming Specifications AC Chip-Level Specifications AC Electrical CharacteristicsDC24M PLL EnableGain 32K SelectAC Gpio Specifications Symbol Description Min Typ Max Units AC General Purpose IO SpecificationsPin Specification minimums for AC Operational Amplifier SpecificationsBW OA NV/rt-Hz Document Number 38-12011 Rev. *GMHz High Opamp Bias not supported Crcprs AC Digital Block SpecificationsSpim SpisLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC Analog Output Buffer SpecificationsBW OB AC Programming Specifications AC External Clock SpecificationsAC I2C Specifications Pin 300-Mil Pdip Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D 51-85079 *C Typical Package Capacitance on Crystal Pins Capacitance on Crystal PinsThermal Impedances Thermal Impedances per PackageOrdering Code Definitions Ordering InformationWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History Orig. Submission Description of Change Date

CY8C24123, CY8C24423, CY8C24223 specifications

The Cypress CY8C24223, CY8C24423, and CY8C24123 are members of the PSoC (Programmable System-on-Chip) family, which combine a microcontroller with configurable analog and digital blocks. These devices are designed for a variety of embedded applications, offering versatility and performance for developers looking to create custom solutions.

One of the standout features of the CY8C24223, CY8C24423, and CY8C24123 is their programmable analog and digital components. These include operational amplifiers, comparators, and even CapSense technology, enabling touch sensing capabilities. This flexibility allows engineers to configure the chip according to the specific needs of their application, thereby reducing the number of external components required and simplifying PCB design.

The microcontroller core in these PSoC devices is a 16-bit architecture, offering a balance between performance and power efficiency. The CY8C24223 and CY8C24423 variants include higher RAM and Flash memory options, catering to more demanding applications compared to the CY8C24123. This makes them suitable for tasks ranging from simple control operations to more complex computational processes.

A key technology utilized in these devices is the integrated programmable interconnect, which allows for easy communication between the various configurable blocks. This feature significantly speeds up the development process by enabling designers to create custom peripheral setups without the need for extensive coding.

In addition to their hardware features, Cypress provides an intuitive design environment called PSoC Creator. This IDE simplifies the process of configuring the device, allowing developers to drag and drop components into a design schematic and generate code effortlessly. PSoC Creator also includes simulation features, enabling testing and validation of designs before deployment.

The PSoC family is known for its low power consumption, which is crucial for battery-operated devices. The power management features integrated into these models allow for various operational modes, making them energy-efficient and ideal for portable applications.

In summary, the Cypress CY8C24223, CY8C24423, and CY8C24123 are powerful and flexible programmable system-on-chip solutions. With a combination of configurable analog and digital blocks, solid performance specifications, and an easy-to-use development environment, these devices stand out for engineers working on innovative embedded applications across numerous industries. Their low power consumption further enhances their appeal for modern applications, making them a strong choice for designers.