Cypress CY8C24423, CY8C24123, CY8C24223 manual AC I2C Specifications

Page 35

CY8C24123

CY8C24223, CY8C24423

AC I2C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only or unless otherwise specified.

Table 35. AC Characteristics of the I2C SDA and SCL Pins

Symbol

Description

Standard Mode

Fast Mode

Units

Min

Max

Min

Max

 

 

 

FSCLI2C

SCL Clock Frequency

0

100

0

400

kHz

THDSTAI2C

Hold Time (repeated) START Condition. After this period, the first

4.0

–

0.6

–

μs

 

clock pulse is generated.

 

 

 

 

 

TLOWI2C

LOW Period of the SCL Clock

4.7

–

1.3

–

μs

THIGHI2C

HIGH Period of the SCL Clock

4.0

–

0.6

–

μs

TSUSTAI2C

Setup Time for a Repeated START Condition

4.7

–

0.6

–

μs

THDDATI2C

Data Hold Time

0

–

0

–

μs

TSUDATI2C

Data Setup Time

250

–

100a

–

ns

TSUSTOI2C

Setup Time for STOP Condition

4.0

–

0.6

–

μs

TBUFI2C

Bus Free Time Between a STOP and START Condition

4.7

–

1.3

–

μs

TSPI2C

Pulse Width of spikes are suppressed by the input filter.

–

–

0

50

ns

a.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

Figure 18. Definition for Timing for Fast/Standard Mode on the I2C Bus

SDA

TLOWI2C

 

 

 

TSUDATI2C

 

 

 

 

SCL

 

 

 

S

THDSTAI2C THDDATI2C

THIGHI2C

TSUSTAI2C

THDSTAI2C

Sr

TSPI2C

TSUSTOI2C

TBUFI2C

P S

Document Number: 38-12011 Rev. *G

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Digital System PSoC Functional OverviewPSoC Core Analog System Analog System Block DiagramAdditional System Resources PSoC Device CharacteristicsGetting Started Design Browser Development ToolsPSoC Designer Software Subsystems Device EditorOnline Help System User Modules and the PSoC Development ProcessHardware Tools DebuggerDocument Conventions Pin Part Pinout PinoutsSCL Switch Mode Pump SMP connection toActive high external reset with internal External components requiredExtclk Pin Part Pinout MLF Type Description Digital Analog NameAbbreviations Used Register ReferenceRegister Conventions Register Mapping TablesRegister Map Bank 0 Table User Space Name Addr 0,Hex AccessName Addr 1,Hex Access Register Map Bank 1 Table Configuration SpaceCY8C24123 CY8C24223, CY8C24423 Units of Measure Symbol Unit of Measure Electrical SpecificationsAbsolute Maximum Ratings Operating TemperatureAbsolute Maximum Ratings Symbol Description Min Typ Units Operating Temperature Symbol Description Min Typ Max UnitsDC Chip-Level Specifications DC Electrical CharacteristicsDC Operational Amplifier Specifications DC General Purpose IO SpecificationsDC Gpio Specifications Symbol Description Min Typ Max Units Psrr OA Vdd Power = Low Power = Medium Power = High is 5V only Input Capacitance Port 0 Analog Pins Package and pinPower = Low At high power. For all Power = Medium Power = High High power, high opampPsrr OB DC Analog Output Buffer SpecificationsPSoCTM DC Switch Mode Pump SpecificationsBAT5V BAT3VVdd/2 BG + DC Analog Reference SpecificationsVdd/2 + BG + Bandgap Voltage Reference Agnd = Vdd/2 a CT Block Power = HighCT Block Power = High Agnd = P24 P24 = Vdd/2 DC POR and LVD Specifications DC Analog PSoC Block SpecificationsDC Programming Specifications DC24M AC Electrical CharacteristicsAC Chip-Level Specifications 32K Select EnablePLL GainPin AC General Purpose IO SpecificationsAC Gpio Specifications Symbol Description Min Typ Max Units NV/rt-Hz Document Number 38-12011 Rev. *G AC Operational Amplifier SpecificationsSpecification minimums for BW OAMHz High Opamp Bias not supported Spis AC Digital Block SpecificationsCrcprs SpimBW OB AC Analog Output Buffer SpecificationsLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC Programming Specifications AC External Clock SpecificationsAC I2C Specifications Pin 300-Mil Pdip Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D 51-85079 *C Thermal Impedances per Package Capacitance on Crystal PinsTypical Package Capacitance on Crystal Pins Thermal ImpedancesOrdering Code Definitions Ordering InformationOrig. Submission Description of Change Date Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History

CY8C24123, CY8C24423, CY8C24223 specifications

The Cypress CY8C24223, CY8C24423, and CY8C24123 are members of the PSoC (Programmable System-on-Chip) family, which combine a microcontroller with configurable analog and digital blocks. These devices are designed for a variety of embedded applications, offering versatility and performance for developers looking to create custom solutions.

One of the standout features of the CY8C24223, CY8C24423, and CY8C24123 is their programmable analog and digital components. These include operational amplifiers, comparators, and even CapSense technology, enabling touch sensing capabilities. This flexibility allows engineers to configure the chip according to the specific needs of their application, thereby reducing the number of external components required and simplifying PCB design.

The microcontroller core in these PSoC devices is a 16-bit architecture, offering a balance between performance and power efficiency. The CY8C24223 and CY8C24423 variants include higher RAM and Flash memory options, catering to more demanding applications compared to the CY8C24123. This makes them suitable for tasks ranging from simple control operations to more complex computational processes.

A key technology utilized in these devices is the integrated programmable interconnect, which allows for easy communication between the various configurable blocks. This feature significantly speeds up the development process by enabling designers to create custom peripheral setups without the need for extensive coding.

In addition to their hardware features, Cypress provides an intuitive design environment called PSoC Creator. This IDE simplifies the process of configuring the device, allowing developers to drag and drop components into a design schematic and generate code effortlessly. PSoC Creator also includes simulation features, enabling testing and validation of designs before deployment.

The PSoC family is known for its low power consumption, which is crucial for battery-operated devices. The power management features integrated into these models allow for various operational modes, making them energy-efficient and ideal for portable applications.

In summary, the Cypress CY8C24223, CY8C24423, and CY8C24123 are powerful and flexible programmable system-on-chip solutions. With a combination of configurable analog and digital blocks, solid performance specifications, and an easy-to-use development environment, these devices stand out for engineers working on innovative embedded applications across numerous industries. Their low power consumption further enhances their appeal for modern applications, making them a strong choice for designers.
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