Cypress CY8C24423, CY8C24123 manual DC Electrical Characteristics, DC Chip-Level Specifications

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CY8C24123

CY8C24223, CY8C24423

DC Electrical Characteristics

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only or unless otherwise specified.

Table 13. DC Chip-Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Vdd

Supply Voltage

3.00

–

5.25

V

 

IDD

Supply Current

–

5

8

mA

Conditions are Vdd = 5.0V, 25 oC,

 

 

 

 

 

 

 

CPU = 3 MHz, 48 MHz disabled. VC1

 

 

 

 

 

 

 

= 1.5 MHz, VC2 = 93.75 kHz,

 

 

 

 

 

 

 

VC3 = 93.75 kHz.

I

 

Supply Current

–

3.3

6.0

mA

Conditions are Vdd = 3.3V, T = 25

 

DD3

 

 

 

 

 

oC, CPU = 3 MHz, 48 MHz =A

 

 

 

 

 

 

 

Disabled, VC1 = 1.5 MHz,

 

 

 

 

 

 

 

VC2 = 93.75 kHz, VC3 = 93.75 kHz.

ISB

Sleep (Mode) Current with POR, LVD,

–

3

6.5

μA

Conditions are with internal slow

 

 

Sleep Timer, and WDT.a

 

 

 

 

speed oscillator, Vdd = 3.3V, -40 oC

 

 

 

 

 

 

 

<= TA <= 55 oC.

ISBH

Sleep (Mode) Current with POR, LVD,

–

4

25

μA

Conditions are with internal slow

 

 

Sleep Timer, and WDT at high temper-

 

 

 

 

speed oscillator, Vdd = 3.3V,

 

 

ature.a

 

 

 

 

55 oC < TA <= 85 oC.

ISBXTL

Sleep (Mode) Current with POR, LVD,

–

4

7.5

μA

Conditions are with properly loaded,

 

 

Sleep Timer, WDT, and external crystal.a

 

 

 

 

1 μW max, 32.768 kHz crystal. Vdd

 

 

 

 

 

 

 

= 3.3V, -40 oC <= TA <= 55 oC.

ISBXTLH

Sleep (Mode) Current with POR, LVD,

–

5

26

μA

Conditions are with properly loaded,

 

 

Sleep Timer, WDT, and external crystal at

 

 

 

 

1μW max, 32.768 kHz crystal.

 

 

high temperature.a

 

 

 

 

Vdd = 3.3 V, 55 oC < T <= 85 oC.

 

 

 

 

 

 

 

A

VREF

Reference Voltage (Bandgap)

1.275

1.3

1.325

V

Trimmed for appropriate Vdd.

a.Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled.

Document Number: 38-12011 Rev. *G

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Digital System PSoC Functional OverviewPSoC Core Analog System Analog System Block DiagramAdditional System Resources PSoC Device CharacteristicsGetting Started PSoC Designer Software Subsystems Development ToolsDevice Editor Design BrowserHardware Tools User Modules and the PSoC Development ProcessDebugger Online Help SystemDocument Conventions Pin Part Pinout PinoutsActive high external reset with internal Switch Mode Pump SMP connection toExternal components required SCLExtclk Pin Part Pinout MLF Type Description Digital Analog NameRegister Conventions Register ReferenceRegister Mapping Tables Abbreviations UsedRegister Map Bank 0 Table User Space Name Addr 0,Hex AccessName Addr 1,Hex Access Register Map Bank 1 Table Configuration SpaceCY8C24123 CY8C24223, CY8C24423 Units of Measure Symbol Unit of Measure Electrical SpecificationsAbsolute Maximum Ratings Symbol Description Min Typ Units Operating TemperatureOperating Temperature Symbol Description Min Typ Max Units Absolute Maximum RatingsDC Chip-Level Specifications DC Electrical CharacteristicsDC Operational Amplifier Specifications DC General Purpose IO SpecificationsDC Gpio Specifications Symbol Description Min Typ Max Units Psrr OA Power = Low At high power. For all Power = Medium Input Capacitance Port 0 Analog Pins Package and pinPower = High High power, high opamp Vdd Power = Low Power = Medium Power = High is 5V onlyPsrr OB DC Analog Output Buffer SpecificationsBAT5V DC Switch Mode Pump SpecificationsBAT3V PSoCTMVdd/2 BG + DC Analog Reference SpecificationsVdd/2 + BG + Bandgap Voltage Reference Agnd = Vdd/2 a CT Block Power = HighCT Block Power = High Agnd = P24 P24 = Vdd/2 DC POR and LVD Specifications DC Analog PSoC Block SpecificationsDC Programming Specifications DC24M AC Electrical CharacteristicsAC Chip-Level Specifications PLL EnableGain 32K SelectPin AC General Purpose IO SpecificationsAC Gpio Specifications Symbol Description Min Typ Max Units Specification minimums for AC Operational Amplifier SpecificationsBW OA NV/rt-Hz Document Number 38-12011 Rev. *GMHz High Opamp Bias not supported Crcprs AC Digital Block SpecificationsSpim SpisBW OB AC Analog Output Buffer SpecificationsLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC Programming Specifications AC External Clock SpecificationsAC I2C Specifications Pin 300-Mil Pdip Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D 51-85079 *C Typical Package Capacitance on Crystal Pins Capacitance on Crystal PinsThermal Impedances Thermal Impedances per PackageOrdering Code Definitions Ordering InformationWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History Orig. Submission Description of Change Date

CY8C24123, CY8C24423, CY8C24223 specifications

The Cypress CY8C24223, CY8C24423, and CY8C24123 are members of the PSoC (Programmable System-on-Chip) family, which combine a microcontroller with configurable analog and digital blocks. These devices are designed for a variety of embedded applications, offering versatility and performance for developers looking to create custom solutions.

One of the standout features of the CY8C24223, CY8C24423, and CY8C24123 is their programmable analog and digital components. These include operational amplifiers, comparators, and even CapSense technology, enabling touch sensing capabilities. This flexibility allows engineers to configure the chip according to the specific needs of their application, thereby reducing the number of external components required and simplifying PCB design.

The microcontroller core in these PSoC devices is a 16-bit architecture, offering a balance between performance and power efficiency. The CY8C24223 and CY8C24423 variants include higher RAM and Flash memory options, catering to more demanding applications compared to the CY8C24123. This makes them suitable for tasks ranging from simple control operations to more complex computational processes.

A key technology utilized in these devices is the integrated programmable interconnect, which allows for easy communication between the various configurable blocks. This feature significantly speeds up the development process by enabling designers to create custom peripheral setups without the need for extensive coding.

In addition to their hardware features, Cypress provides an intuitive design environment called PSoC Creator. This IDE simplifies the process of configuring the device, allowing developers to drag and drop components into a design schematic and generate code effortlessly. PSoC Creator also includes simulation features, enabling testing and validation of designs before deployment.

The PSoC family is known for its low power consumption, which is crucial for battery-operated devices. The power management features integrated into these models allow for various operational modes, making them energy-efficient and ideal for portable applications.

In summary, the Cypress CY8C24223, CY8C24423, and CY8C24123 are powerful and flexible programmable system-on-chip solutions. With a combination of configurable analog and digital blocks, solid performance specifications, and an easy-to-use development environment, these devices stand out for engineers working on innovative embedded applications across numerous industries. Their low power consumption further enhances their appeal for modern applications, making them a strong choice for designers.
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