Cypress CY7C0830AV, CY7C0837AV, CY7C0832BV, CY7C0833AV, CY7C0832AV, CY7C0831AV manual Document History

Page 27

CY7C0837AV, CY7C0830AV

CY7C0831AV, CY7C0832AV

CY7C0832BV, CY7C0833AV

Document History Page

Document Title: CY7C0837AV/CY7C0830AV/CY7C0831AV/CY7C0832AV/CY7C0832BV/CY7C0833AV, FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM

Document Number: 38-06059

Rev.

ECN No.

Orig. of

Submission

Description of Change

Change

Date

 

 

 

 

 

 

 

 

**

111473

DSG

11/27/01

Change from Spec number: 38-01056 to 38-06059

 

 

 

 

 

*A

111942

JFU

12/21/01

Updated capacitance values

 

 

 

 

Updated switching parameters and ISB3

 

 

 

 

Updated “Read-to-Write-to-Read (OE Controlled)” waveform

 

 

 

 

Revised static discharge voltage

 

 

 

 

Revised footnote regarding ISB3

*B

113741

KRE

04/02/02

Updated Isb values

 

 

 

 

Updated ESD voltage

 

 

 

 

Corrected 0853 pins L3 and L12

*C

114704

KRE

04/24/02

Added discussion of Pause/Restart for JTAG boundary scan

 

 

 

 

 

*D

115336

KRE

07/01/02

Revised speed offerings for all densities

 

 

 

 

 

*E

122307

RBI

12/27/02

Power up requirements added to Maximum Ratings Information

 

 

 

 

 

*F

123636

KRE

1/27/03

Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns

 

 

 

 

 

*G

126053

SPN

08/11/03

Separated out 4M and 9M data sheets

 

 

 

 

Updated Isb and ICC values

*H

129443

RAZ

11/03/03

Updated Isb and ICC values

 

 

 

 

 

*I

231993

YDT

See ECN

Removed “A particular port can write to a certain location while another port is

 

 

 

 

reading that location.” from Functional Description.

*J

231813

WWZ

See ECN

Removed x36 devices (CY7C0852/CY7C0851) from this datasheet. Added

 

 

 

 

0.5M, 1M and 9M x18 devices to it. Changed title to FLEx18 3.3V

 

 

 

 

32K/64K/128K/256K/512K x18 Synchronous Dual-Port RAM. Changed

 

 

 

 

datasheet to accommodate the removals and additions. Removed general

 

 

 

 

JTAG description. Updated JTAG ID codes for all devices. Added 144FBGA

 

 

 

 

package for all devices. Updated selection guide table and moved to the front

 

 

 

 

page. Updated block diagram to reflect x18 configuration. Added preliminary

 

 

 

 

status back due to the addition of the new devices.

*K

311054

RYQ

See ECN

Minor Change: Correct the revision indicated on the footer.

 

 

 

 

 

*L

329111

SPN

See ECN

Updated Marketing part numbers

 

 

 

 

Updated tRSF

*M

330561

RUY

See ECN

Added Byte Select Operation Table

 

 

 

 

 

*N

375198

YDT

See ECN

Removed Preliminary status

 

 

 

 

Added ISB5

 

 

 

 

Changed tRSCNTINT to 10ns

*O

391525

SPN

See ECN

Updated Counter reset section to reflect what is loaded into the mirror register

 

 

 

 

 

*P

414109

LIJ

See ECN

Corrected Ordering Codes for 0831 devices in the 133 Mhz speed bin.

 

 

 

 

Added CY7C0833AV-133BBI.

*Q

461113

YDT

SEE ECN

Changed VDDIO to VDD (typo)

 

 

 

 

Added lead(Pb)-free parts

 

 

 

 

Corrected typo in DC table

*R

2544945

VKN/AESA

07/29/08

Updated Template. Updated ordering information

 

 

 

 

 

*S

2668478

VKN/PYRS

02/04/09

Added CY7C0832BV part

 

 

 

 

Added footnote #1

 

 

 

 

Updated Ordering information table

Document #: 38-06059 Rev. *S

Page 27 of 28

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Contents Functional Description FeaturesMirror Reg Logic Block DiagramTrue RAM ArrayDQ9 L DQ9 R Pin ConfigurationsCE1L Byte Select Operation Pin DefinitionsInterrupt Operation Example 2, 12, 13, 14, 15 Master ResetMailbox Interrupts Address Counter and Mask Register OperationsCounter Hold Operation Counter Reset OperationCounter Load Operation Counter Increment OperationCounting by Two Mask Reset OperationRetransmit Mask Readback OperationCLK Cnten ADS Cntrst MrstBoundary Scan Hierarchy for 9-Mbit Device Performing a TAP ResetIeee 1149.1 Serial Boundary Scan Jtag Performing a Pause/RestartScan Registers Sizes Register Name Bit Size Instruction Identification CodesInstruction Code Description Capacitance Electrical CharacteristicsMaximum Ratings Operating RangeSwitching Characteristics Master Reset Timing DelaysJtag Timing and Switching Waveforms Read Cycle12, 30, 31, 32 Switching WaveformsBank Select Read34 Read-to-Write-to-Read OE Controlled33, 36, 38 Write with Address Counter Advance39 Readback State of Address Counter or Mask Register43, 44, 45 Rport LportCounter Interrupt and Retransmit 15, 42, 50, 51, 52 Read Outputs DisabledDeselected Write64K × 18 1M 3.3V Synchronous CY7C0830AV Dual-Port Sram Ordering Information512K × 18 9M 3.3V Synchronous CY7C0833AV Dual-Port Sram 128K × 18 2M 3.3V Synchronous CY7C0831AV Dual-Port Sram32K × 18 512K 3.3V Synchronous CY7C0837AV Dual-Port Sram Package DiagramsPin Thin Quad Flatpack 14 x 14 x 1.4 mm Document History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB

CY7C0837AV, CY7C0833AV, CY7C0831AV, CY7C0830AV, CY7C0832AV specifications

Cypress Semiconductor, a leader in innovative semiconductor solutions, has developed a range of high-performance SRAM (Static Random Access Memory) products, including the CY7C0837AV, CY7C0833AV, CY7C0831AV, CY7C0830AV, and CY7C0832AV. These devices cater to various applications requiring fast, reliable memory storage.

One of the main features of these SRAMs is their speed. They offer fast access times, which range from 10 to 15 nanoseconds. This rapid access is critical for applications where speed is essential, such as high-speed networking and telecommunications equipment, automotive systems, and industrial controls. The CY7C0837AV, for instance, boasts a 1 Mbit memory capacity, making it suitable for applications requiring a larger data buffer.

Another notable feature of these devices is their low power consumption. The SRAMs are designed to operate at low voltages, typically around 3.3V, which greatly reduces the overall power requirements. This characteristic is particularly advantageous for battery-operated devices and portable electronics, as it extends battery life and improves energy efficiency.

Cypress's SRAM offerings incorporate advanced technologies like asynchronous read and write operations, which enable users to access memory without the need for a clock signal. This asynchronous nature allows for simpler system designs and integration, significantly reducing component count and complexity.

In terms of packaging, these SRAMs are available in various formats, including standard DIP and surface-mount options, facilitating easy integration into a range of printed circuit boards. Their footprint and compatibility with existing designs ensure they can be utilized in both new developments and legacy system enhancements.

The CY7C0837AV, CY7C0833AV, CY7C0831AV, CY7C0830AV, and CY7C0832AV also support burst mode operations, allowing for faster sequential data access. This feature enhances performance in applications that require continuous data streams, such as video processing and signal processing tasks.

In summary, the Cypress CY7C0837AV, CY7C0833AV, CY7C0831AV, CY7C0830AV, and CY7C0832AV SRAMs provide a combination of high speed, low power consumption, and versatile packaging options. Their advanced technologies and characteristics make them ideal for a wide range of applications, from automotive to industrial systems, solidifying their position as reliable memory solutions in the semiconductor market.