Cypress CY7C0833AV, CY7C0837AV, CY7C0832BV, CY7C0830AV, CY7C0832AV manual Delays, Master Reset Timing

CY7C0837AV, CY7C0830AV

CY7C0831AV, CY7C0832AV

CY7C0832BV, CY7C0833AV

Switching Characteristics (continued)

Over the Operating Range

								-167			-133			-100
								CY7C0837AV		CY7C0837AV
										CY7C0830AV
								CY7C0830AV
Parameter						Description				CY7C0831AV		CY7C0833AV		CY7C0833AV		Unit
								CY7C0831AV
										CY7C0832AV
								CY7C0832AV
										CY7C0832BV
								Min	Max	Min	Max	Min	Max	Min	Max
tHCM		CNT/MSK			Hold Time			0.6		0.6		NA		NA		ns
tOE		Output Enable to Data Valid							4.0		4.4		4.7		5.0	ns
tOLZ[28,29]		OE	to Low Z					0		0						ns
tOHZ[28,29]		OE	to High Z					0	4.0	0	4.4		4.7		5.0	ns
tCD2		Clock to Data Valid							4.0		4.4		4.7		5.0	ns
tCA2		Clock to Counter Address Valid							4.0		4.4		NA		NA	ns
tCM2		Clock to Mask Register Readback Valid							4.0		4.4		NA		NA	ns
tDC		Data Output Hold After Clock HIGH						1.0		1.0		1.0		1.0		ns
tCKHZ[28,29]		Clock HIGH to Output High Z						0	4.0	0	4.4		4.7		5.0	ns
tCKLZ[28, 29]		Clock HIGH to Output Low Z						1.0	4.0	1.0	4.4	1.0	4.7	1.0	5.0	ns
tSINT		Clock to		INT		Set Time		0.5	6.7	0.5	7.5	0.5	7.5	0.5	10	ns
tRINT		Clock to		INT		Reset Time		0.5	6.7	0.5	7.5	0.5	7.5	0.5	10	ns
tSCINT		Clock to		CNTINT			Set Time	0.5	5.0	0.5	5.7	NA	NA	NA	NA	ns
tRCINT		Clock to		CNTINT			Reset time	0.5	5.0	0.5	5.7	NA	NA	NA	NA	ns
Port to Port	Delays
tCCS		Clock to Clock Skew						5.2		6.0		6.0		8.0		ns
Master Reset Timing
tRS		Master Reset Pulse Width						7.0		7.5		7.5		10		ns
tRS		Master Reset Setup Time						6.0		6.0		6.0		8.5		ns
tRSR		Master Reset Recovery Time						6.0		7.5		7.5		10		ns
tRSF		Master Reset to Outputs Inactive							10.0		10.0		10.0		10.0	ns
tRSCNTINT		Master Reset to Counter Interrupt Flag							10.0		10.0		NA		NA	ns
		Reset Time

Notes

28.This parameter is guaranteed by design, but is not production tested.

29.Test conditions used are Load 2.

Document #: 38-06059 Rev. *S Page 14 of 28

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