Hayes Microcomputer Products RCV56HCF manual Base Address Register

Page 61

RCV56HCF PCI/CardBus Modem Designer’s Guide

5.1.5 Revision ID Field

Initial part hardwired to 00.

5.1.6 Class Code Field

Hardwired to 0x078000 to indicate communications controller.

5.1.7 Latency Timer Register

The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. This register has 5 read/write bits (MSBs) plus 3 bits of hardwired zero (LSBs). The Latency Timer Register is loaded into the PCI Latency counter each time FRAME# is asserted to determine how long the master is allowed to retain control of the PCI bus. This register is loaded by system software. The default value for Latency Timer is 00.

5.1.8 Header Type Field

Hardwired to 00.

5.1.9 CIS Pointer Register

This register points to the CIS memory located in the BIF’s memory space.

5.1.10 Subsystem Vendor ID and Subsystem ID Registers

Subsystem Vendor ID and Subsystem ID are optional registers that are implemented in this design. Both registers are loaded from the serial EEPROM after RST#.

5.1.11 Interrupt Line Register

The Interrupt Line register is an eight bit register that is read/write. POST software will write the value of this register as it initializes and configures the system. The value in this register indicates which of the system interrupt controllers the device’s interrupt pin is connected to.

5.1.12 Interrupt Pin Register

The Interrupt Pin register tells which interrupt pin the device uses. The value of this register will be 0x01, indicating that INTA# will be used.

5.1.13 Min Grant and Max Latency Registers

The Min Grant and Max Latency registers are used to specify the devices desired settings for Latency Timer values. For both registers, the value specifies a period of time in units of ¼ microsecond. Min Grant is used for specifying the desired burst period assuming a 33 MHz clock. Min Latency specifies how often the device needs to gain access to the PCI bus. These registers are loaded from the serial EEPROM after RST#.

5.2 BASE ADDRESS REGISTER

BIF provides a single Base Address Register. The Base Address Register is a 32 bit register that is used to access the BIF register set. Bits 3:0 are hard-wired to 0 to indicate memory space. Bits 15-4 will be hard-wired to 0. The remaining bits (31 -

16)will be read/write. This specifies that this device requires a 64k byte address space. After reset, the Base Address Register contains 0x00000000.

The 64k byte address space used by the BIF is divided into 4k byte regions. Each 4k byte region is used as Table 5-4.

Table 5-4. BIF Address Map

Address

Address

Region Name

Description

[15:12]

[11:0]

 

 

0x0

0x0-0xfff

BASIC2 Registers

Buffers, control, and status registers

0x1

0x0-0xfff

CIS Memory

Data loaded from Serial EEPROM for Card Bus applications

 

 

 

 

0x2

0x0-0xfff

DSP Scratch Pad

Access to DSP scratch page registers

0x3

0x0-0xfff

Reserved

 

0x4

0x0-0xfff

Reserved

 

 

 

 

 

0x5-0xf

0x0-0xfff

Reserved.

 

1129

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Contents RCV56HCF RCV56HCF PCI/CardBus Modem Designer’s Guide Table of Contents Command SET Rockwell Proprietary Information List of Figures List of Tables Summary FeaturesRCV56HCF PCI/CardBus Modem Designer’s Guide Marketing Modem Models and FunctionsModel Number1 FdspPC Software RCV56HCF Hardware Configuration Block Diagram Data Pump BUS General Description Technical OverviewOperating Modes Downloadable Modem Data Pump Firmware Host-Controlled Modem SoftwareHardware Interfaces RCV56HCF PCI/CardBus Modem Designer’s Guide Typical Audio Signal Interface U.S Relay Positions VoiceView Mode Typical Signal Routing Voice Mode+VLS= VOICE# CIDL1#This page is intentionally blank Establishing Data Modem Connections Data ModeVOICE/AUDIO Mode Error Correction and Data CompressionMNP 10EC Enhanced Cellular Connection FAX Class 1 OperationFULL-DUPLEX Speakerphone Fdsp Mode HOST-BASED Dsvd ModeVoiceview LOW Power Sleep Mode DiagnosticsCaller ID World Class Country SupportHardware Interface Hardware Signal Pins and DefinitionsTqfp 11229 BUS InterfaceRCV56HCF MDP PIN Tqfp R6776Bus Interface 176-Pin Tqfp Hardware Interface Signals Bus Interface 176-Pin Tqfp Pin Signals Pin Signal Label Type1 Interface DEVSEL# System Bus Interface Pin Signal DefinitionsPCI BUS Interface Serial Eeprom Interface NMC93C56 or Equivalent Bus Interface Pin Signal Definitions Cont’dDAA Interface ReservedMDP Interface Isdn Interface Isdn Models Isdn Interface NON-ISDN ModelsMDP 144-Pin Tqfp Hardware Interface Signals MDP 144-Pin Tqfp Pin Signals Pin Signal Label Interface3 Type1 MDP Pin Signals 144-Pin TqfpPllgnd PLL Overhead Signals MDP Pin Signal DefinitionsBIF to MDP Interface MDP to Siemens PSB2186 S/T InterfacePllgnd Connection. Connect to Agnd MDP Signal Definitions ContdModem INTERCONNECT/NO Connect Power and Maximum Ratings ELECTRICAL,SWITCHING,AND Environmental CharacteristicsCurrent and Power Requirements Maximum RatingsPCI Bus AC Specifications for 3.3V Signaling PCI Bus DC Specifications for 3.3V SignalingSymbol Parameter Condition Min Max Units PCI BusParameter Symbol Min Typ Max Units Test Conditions MDP Digital Electrical Characteristics3 MDP Name Type Characteristic Value 10. Analog Electrical CharacteristicsTELINL1 TXA1L1PCI Bus Timing Interface Timing and WaveformsSerial Eeprom Timing 11. Timing Serial Eeprom InterfaceExternal Device Bus Timing Symbol Description Min Typ Max Units Test Conditions Read12. Timing External Device Bus Interface WriteISDNCS# DWR# DD0-DD7 ISDNCS# DRD# DD0-DD713. Timing IOM-2 Interface IOM-2 InterfaceThis page is intentionally blank PC Board Layout Guidelines Component PlacementGeneral Principles Signal Routing Modem Pin Noise Characteristics PowerDevice Function Noise Source Neutral Noise Sensitive MDP VDD, VAACrystal Circuit Ground Planes7 VCL1 and Vref Circuit Optional Configurations CRYSTAL/OSCILLATOR SpecificationsOther Considerations Telephone and Local Handset InterfaceCharacteristic Value Crystal Specifications Surface MountElectrical MechanicalCrystal Specifications Through Hole Package Dimensions 144-Pin Tqfp Package DimensionsRCV56HCF PCI/CardBus Modem Designer’s Guide This page is intentionally blank Vendor ID Field PCI Configuration RegistersDevice ID Field Bit Offset 3124 2316 158 HexStatus Register Command RegisterBit Description Base Address Register Serial Eeprom Interface Eeprom Configuration DataEeprom Address Copied to CIS RAMCommand Set Summary Functional Use Sort Command SETData Compression Command Set Summary Functional Use Sort Cont’dVoice Commands Command Set Summary Alphanumeric Sort Command Set Summary Alphanumeric Sort Cont’d RCV56HCF PCI/CardBus Modem Designer’s Guide Inside Back Cover Regional Sales Offices
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