Hayes Microcomputer Products RCV56HCF manual Signal Routing

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RCV56HCF PCI/CardBus Modem Designer’s Guide

3.Once sections have been roughly defined, place the components starting with the connectors and jacks.

a)Allow sufficient clearance around connectors and jacks for mating connectors and plugs.

b)Allow sufficient clearance around components for power and ground traces.

c)Allow sufficient clearance around sockets to allow the use of component extractors.

4.First, place the mixed analog/digital components (e.g., modem device, A/D converter, and D/A converter).

a)Orient the components so pins carrying digital signals extend onto the digital section and pins carrying analog signals extend onto the analog section as much as possible.

b)Position the components to straddle the border between analog and digital sections.

5.Place all analog components.

a)Place the analog circuitry, including the DAA, on the same area of the PCB.

b)Place the analog components close to and on the side of board containing the TXA1_L1, TXA2_L1, RXA_L1, VC_L1, and VREF signals.

c)Avoid placing noisy components and traces near TXA1_L1, TXA2_L1, RXA_L1, VC_L1, and VREF lines.

6.Place active digital components/circuits and decoupling capacitors.

a)Place digital components close together in order to minimize signal trace length.

b)Place 0.1 µF decoupling (bypass) capacitors close to the pins (usually power and ground) of the IC they are decoupling. Make the smallest loop area possible between the capacitor and power/ground pins to reduce EMI.

c)Place host bus interface components close to the edge connector in accordance with the applicable bus interface standard, e.g., the PCI Bus Specification.

d)Place crystal circuits as close as possible to the devices they drive.

7.Provide a “connector” component, usually a zero ohm resistor or a ferrite bead at one or more points on the PCB to connect one section’s ground to another.

4.1.3 Signal Routing

1.Route the modem signals to provide maximum isolation between noise sources and noise sensitive inputs. When layout requirements necessitate routing these signals together, they should be separated by neutral signals. The noise source, neutral, and noise sensitive pins are listed in Table 4-1.

2.Keep digital signals within the digital section and analog signals within the analog section. (Previous placement of isolation traces should prevent these traces from straying outside their respective sections.) Route the digital traces perpendicular to the analog traces to minimize signal cross coupling.

3.Provide isolation traces (usually ground traces) to ensure that analog signals are confined to the analog section and digital traces remain out of the analog section. A trace may have to be narrowed to route it though a mixed analog/digital IC, but try to keep the trace continuous.

a)Route an analog isolation ground trace, at least 50 mil to 100 mil wide, around the border of the analog section; put on both sides of the PCB.

b)Route a digital isolation ground trace, at least 50 mil to 100 mil wide, and 200 mil wide on one side of the PCB edge, around the border of the digital section.

4.Keep host interface signals (e.g., AEN, IOR#, IOW#, HRESET) traces at least 10 mil thick (preferably 12 - 15 mil).

5.Keep analog signal (e.g., the TXA1_L1, TXA2_L1, RXA_L1, TELIN_L1, TELOUT_L1 , MIC_M, MIC_V, and SPKROUT_M) traces at least 10 mil thick (preferably 12 - 15 mil).

6.Keep all other signal traces as wide as possible, at least 5 mil (preferably 10 mil).Route the signals between components by the shortest possible path (the components should have been previously placed to allow this).

7.Route the traces between bypass capacitors to IC pins, at least 25 mil wide; avoid vias if possible.

8.Gather signals that pass between sections (typically low speed control and status signals) together and route them between sections through a path in the isolation ground traces at one (preferred) or two points only. If the path is made on one side only, then the isolation trace can be kept contiguous by briefly passing it to the other side of the PCB to jump over the signal traces.

9.Avoid right angle (90 degree) turns on high frequency traces. Use smoothed radiuses or 45 degree corners.

4-2

ROCKWELL PROPRIETARY INFORMATION

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Contents RCV56HCF RCV56HCF PCI/CardBus Modem Designer’s Guide Table of Contents Command SET Rockwell Proprietary Information List of Figures List of Tables Features SummaryRCV56HCF PCI/CardBus Modem Designer’s Guide Model Number1 Modem Models and FunctionsMarketing FdspPC Software RCV56HCF Hardware Configuration Block Diagram Data Pump BUS Operating Modes Technical OverviewGeneral Description Hardware Interfaces Host-Controlled Modem SoftwareDownloadable Modem Data Pump Firmware RCV56HCF PCI/CardBus Modem Designer’s Guide Typical Audio Signal Interface U.S +VLS= Typical Signal Routing Voice ModeRelay Positions VoiceView Mode VOICE# CIDL1#This page is intentionally blank Data Mode Establishing Data Modem ConnectionsMNP 10EC Enhanced Cellular Connection Error Correction and Data CompressionVOICE/AUDIO Mode FAX Class 1 OperationVoiceview HOST-BASED Dsvd ModeFULL-DUPLEX Speakerphone Fdsp Mode Caller ID DiagnosticsLOW Power Sleep Mode World Class Country SupportHardware Signal Pins and Definitions Hardware InterfaceRCV56HCF MDP BUS InterfaceTqfp 11229 PIN Tqfp R6776Bus Interface 176-Pin Tqfp Hardware Interface Signals Bus Interface 176-Pin Tqfp Pin Signals Pin Signal Label Type1 Interface DEVSEL# PCI BUS Interface Bus Interface Pin Signal DefinitionsSystem DAA Interface Bus Interface Pin Signal Definitions Cont’dSerial Eeprom Interface NMC93C56 or Equivalent ReservedMDP Interface Isdn Interface NON-ISDN Models Isdn Interface Isdn ModelsMDP 144-Pin Tqfp Hardware Interface Signals MDP 144-Pin Tqfp Pin Signals MDP Pin Signals 144-Pin Tqfp Pin Signal Label Interface3 Type1Pllgnd PLL BIF to MDP Interface MDP Pin Signal DefinitionsOverhead Signals MDP to Siemens PSB2186 S/T InterfaceMDP Signal Definitions Contd Pllgnd Connection. Connect to AgndModem INTERCONNECT/NO Connect Current and Power Requirements ELECTRICAL,SWITCHING,AND Environmental CharacteristicsPower and Maximum Ratings Maximum RatingsSymbol Parameter Condition Min Max Units PCI Bus DC Specifications for 3.3V SignalingPCI Bus AC Specifications for 3.3V Signaling PCI Bus3 MDP MDP Digital Electrical CharacteristicsParameter Symbol Min Typ Max Units Test Conditions TELINL1 10. Analog Electrical CharacteristicsName Type Characteristic Value TXA1L1Serial Eeprom Timing Interface Timing and WaveformsPCI Bus Timing 11. Timing Serial Eeprom Interface12. Timing External Device Bus Interface Symbol Description Min Typ Max Units Test Conditions ReadExternal Device Bus Timing WriteISDNCS# DRD# DD0-DD7 ISDNCS# DWR# DD0-DD7IOM-2 Interface 13. Timing IOM-2 InterfaceThis page is intentionally blank General Principles Component PlacementPC Board Layout Guidelines Signal Routing Device Function Noise Source Neutral Noise Sensitive PowerModem Pin Noise Characteristics MDP VDD, VAA7 VCL1 and Vref Circuit Ground PlanesCrystal Circuit Other Considerations CRYSTAL/OSCILLATOR SpecificationsOptional Configurations Telephone and Local Handset InterfaceElectrical Crystal Specifications Surface MountCharacteristic Value MechanicalCrystal Specifications Through Hole Package Dimensions Package Dimensions 144-Pin TqfpRCV56HCF PCI/CardBus Modem Designer’s Guide This page is intentionally blank Device ID Field PCI Configuration RegistersVendor ID Field Bit Offset 3124 2316 158 HexBit Description Command RegisterStatus Register Base Address Register Eeprom Address Copied to Eeprom Configuration DataSerial Eeprom Interface CIS RAMCommand SET Command Set Summary Functional Use SortCommand Set Summary Functional Use Sort Cont’d Data CompressionVoice Commands Command Set Summary Alphanumeric Sort Command Set Summary Alphanumeric Sort Cont’d RCV56HCF PCI/CardBus Modem Designer’s Guide Inside Back Cover Regional Sales Offices
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