Maxtor 92048D8, 91024D4, 90750D3, 91280D5, 91536D6, 91792D7 manual Write Multiple, Write DMA

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INTERFACE COMMANDS

Write Multiple

Performs similarly to the Write Sector(s) command, except that:

1.The controller sets BSY immediately upon receipt of the command,

2.Data transfers are multiple sector blocks and

3.The Long bit and Retry bit is not valid.

Command execution differs from Write Sector(s) because:

1.Several sectors transfer to the host as a block without intervening interrupts.

2.DRQ qualification of the transfer is required at the start of the block, not on each sector.

The block count consists of the number of sectors to be transferred as a block and is programmed by the Set Multiple Mode command, which must be executed prior to the Write Multiple command. When the Write Multiple command is issued, the Sector Count register contains the number of sectors requested — not the number of blocks or the block count.

If the number of sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. This final, partial block transfer is for N sectors, where N = (sector count) modulo (block count)

The Write Multiple operation will be rejected with an Aborted Command error if attempted:

1.Before the Set Multiple Mode command has been executed, or

2.When Write Multiple commands are disabled.

All disk errors encountered during Write Multiple commands report after the attempted disk write of the block or partial block in which the error occurred.

The write operation ends with the sector in error, even if it was in the middle of a block. When an error occurs, subsequent blocks are not transferred. When DRQ is set at the beginning of each full and partial block, interrupts are generated.

Write DMA

Multi-word DMA

Identical to the Write Sector(s) command, except that:

1.The host initializes a slave-DMA channel prior to issuing the command,

2.Data transfers are qualified by DMARQ and are performed by the slave-DMA channel and

3.The drive issues only one interrupt per command to indicate that data transfer has terminated at status is available.

Ultra DMA

With the Ultra DMA Write protocol, the control signal (HSTROBE) that latches data from DD(15:0) is generated by the devices which drives the data onto the bus. Ownership of DD(15:0) and this data strobe signal are given to the host for an Ultra DMA data out burst.

During an Ultra DMA Write burst, the host always moves data onto the bus, and, after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a HSTROBE edge to latch the data. Both edges of HSTROBE are used for data transfers.

Any error encountered during Write DMA execution results in the termination of data transfer. The drive issues an interrupt to indicate that data transfer has terminated and status is available in the error register. The error posting is the same as that of the Write Sector(s) command.

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Contents HA RD Drive Produc T MA Nual DiamondMax Plus Revisions Manual No U T I O N Before You BeginContents Handling and Installation Product SpecificationsHost Software Interface AT Interface DescriptionGlossary Interface CommandsService and Support Figures Maxtor Corporation IntroductionManual Organization AbbreviationsConventions Signal ConventionsKey Words NumberingProduct Description DiamondMax Plus 5120 Key FeaturesFunctional / Interface Product FeaturesLogical Block Addressing On-the-Fly Hardware Error Correction Code ECCDefect Management Zone DMZ Software ECC CorrectionCache Management Read-Ahead ModeBuffer Segmentation Automatic Write Reallocation AWRMajor HDA Components Jumper Location/Configuration Subsystem ConfigurationCylinder Limitation Dual Drive SupportDrive Configuration Product SpecificationsPerformance Specifications Models and CapacitiesParameter Standard Metric Physical DimensionsPower Mode Definitions Power RequirementsEPA Energy Star Compliance Environmental LimitsShock and Vibration Reliability SpecificationsCanadian Emissions Statement Safety Regulatory ComplianceRadiated Electromagnetic Field Emissions EMC Compliance Hard Drive Handling Precautions Handling and InstallationPre-formatted Drive Important NoticeMulti-pack Shipping Container Unpacking and InspectionRepacking Physical InstallationRecommended Mounting Configuration Before You Begin General Requirements Mounting Drive in System Attaching Interface Power Cables System Setup Hard Drive Preparation System Hangs During Boot Signal Interface ConnectorAT Interface Description Pin Description SummaryPin Description Table PIN Name Signal Name Signal DescriptionPIO Timing Timing Parameters ModeDMA Timing Timing Parameters all times in nanoseconds Ultra DMA TimingSustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst Features Register Error RegisterHost Software Interface Task File RegistersSector Number Register Sector Count RegisterCylinder Number Registers Device/Head RegisterCommand Register Summary Command Name Command Code Parameters Used SDHAlternate Status Register Control Diagnostic RegistersDevice Control Register Digital Input RegisterInterrupt Handling Reset and Interrupt HandlingReset Handling Set Feature Commands Interface CommandsRead Verify Sectors Read CommandsRead Sectors Read Multiple Read DMASet Multiple Mode Write CommandsWrite Sectors Write Verify SectorsWrite DMA Write MultipleSet Features Mode Set Feature CommandsPower Mode Commands Sleep Mode Identify Drive Initialization Commands15-8 = PIO data transfer mode = Write Cache enabled Initialize Drive Parameters Format Track Seek, Format and Diagnostic CommandsExecute Drive Diagnostic Execute S.M.A.R.T A.R.T. Command SetService Policy Service and SupportNo Quibble Service SupportInternet MaxFax ServiceCustomer Service Glossary Direct Memory Access Direct AccessError Correction Code ECC Error FreeHead Disk Assembly HDA Hard ErrorFile Allocation Table FAT Flux Changes PER InchLogical Address Phase Locked Loop PLLLogical Block Addressing Logical SectorRead Gate Signal Random Access Memory RAMRecoverable Error Sector Pulse SignalUnrecoverable Error UN-CORRECTABLE ErrorWrite Gate Signal THIN-FILM Media
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