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Operation
Model:
Master Clock: 50 MHz, M= 20 nsec
Pixel Clock: 25 MHz, P= 40 nsec
1. Pixel Clock and Digital Data
Pixel Clock
A
Data
Tcd
Tcd: Clock to Data Ready
Tdc: Data Ready to Next Clock
Thd: Data Hold Time
Operation Mode: 15 Frame /sec
TdcT | hd |
Tcd = 28 nsec, Tdc = 12 nsec, Thd = 10 nsec.
2. Horizontal Signals | fHD = [ 15.55 | KHz] |
| tHD = [ 64.32 | µsec] |
External HD
[ 3 P], (120 ns) |
|
|
Internal HD | A [ 1447 P], | (57.88 µs) |
|
| |
| B [ 1608 P], (64.32 µs) | |
C [12 P], (480 ns) |
|
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| D [ 216 P], (8.64 µs) | |
LDV | E [ 1392 P], (55.68 µs) | |
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| F [ 1608 P], (64.32 µs) | |
Digital Data |
|
|
| G [ 1392 P], (55.68 µs) | |
Analog Video | H [ 216 P], (8.64 µs) |
|
| K [ 1392 P], (55.68 µs) | |
I [ 48 P], (1.92 µs) | L [ 61 P], (2.44 µs) | |
| ||
| J [ 168 P], (6.72 µs) |
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