National Products DS90C3202 manual General Description, Features, Block Diagram

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September 2006

DS90C3202

3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

DS90C3202 3.

General Description

The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3202 is designed to interface between the digital video processor and the display device using the low-power, low-EMI LVDS (Low Voltage Differential Signal- ing) interface. The DS90C3202 converts up to ten LVDS data streams back into 70 bits of parallel LVCMOS/LVTTL data. The receiver can be programmed with rising edge or falling edge clock. Optional wo-wire serial programming al- lows fine tuning in development and production environ- ments. With an input clock at 135 MHz, the maximum trans- mission rate of each LVDS line is 945 Mbps, for an aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This allows the dual 10-bit LVDS Receiver to support resolutions up to HDTV.

Features

nUp to 9.45 Gbit/s data throughput

n8 MHz to 135 MHz input clock support n Supports up to QXGA panel resolutions

n Supports HDTV panel resolutions and frame rates up to 1920 x 1080p

n LVDS 30-bit, 24-bit or 18-bit color data inputs n Supports single pixel and dual pixel interfaces n Supports spread spectrum clocking

n Two-wire serial communication interface

n Programmable clock edge and control strobe select n Power down mode

n +3.3V supply voltage

n 128-pin TQFP Package

n Compliant to TIA/EIA-644-A-2001 LVDS Standard

3V 8 MHz to 135 MHz Dual

Block Diagram

20147101

FIGURE 1. Receiver Block Diagram

FPD-Link Receiver

© 2006 National Semiconductor Corporation

DS201471

www.national.com

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Contents Block Diagram FeaturesGeneral Description Functional Description Typical Application DiagramLvds Receiver DC Specifications Electrical CharacteristicsAbsolute Maximum Ratings Note Recommended Operating ConditionsReceiver Supply Current Symbol Parameter Conditions Min Typ Max UnitsSymbol Parameter Condition Min Typ Max Units Reference Receiver Switching CharacteristicsAC Timing Diagrams Two-Wire Serial Communication InterfaceWorst Case Test Pattern Receiver Phase Lock Loop Wake-up Time Receiver Input Tolerance and Sampling Window RFB Lvttl Level Programmable Strobe SelectRegisterAddress 29d/1dh bit 21 = 00b Receiver Rsrc and Rhrc Output Setup/Hold Time PTO Enabled20147115 Lvds Input Mapping Receiver Ritol Min and Max DS90C3202 Receiver Pin DiagramPin No Pin Name Pin Type Description DS90C3202 Pin DescriptionsDS90C3202 Pin Descriptions RXOA4 Lvttl O/P Communicating with the DS90C3202 Control Registers Two-Wire Serial Communication Interface DescriptionReset DS90C3202 Two-Wire Serial Interface Register TableBit # Description Default Value AddressBit # Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver