National Products DS90C3202 manual Bit # Description

Page 20

DS90C3202

DS90C3202 Two-Wire Serial Interface Register Table

(Continued)

 

 

 

 

 

 

 

Address

R/W

RESET

Bit #

Description

 

Default Value

 

 

 

 

 

 

 

26d/1ah

R/W

None

[7]

Reserved

 

0000_0000

 

 

 

 

 

 

 

 

 

[6:4]

LVDS input skew control for RXE channel B,

 

 

 

 

 

000 (default) applies to no delay added, ONE buffer

 

 

 

 

 

delay per step adjustment towards Thold improvements

 

 

 

 

 

 

 

 

 

 

 

[3]

Reserved

 

 

 

 

 

 

 

 

 

 

 

[2:0]

LVDS input skew control for RXE channel C,

 

 

 

 

 

000 (default) applies to no delay added, ONE buffer

 

 

 

 

 

delay per step adjustment towards Thold improvements

 

 

 

 

 

 

 

 

27d/1bh

R/W

None

[7]

Reserved

 

0000_0000

 

 

 

 

 

 

 

 

 

[6:4]

LVDS input skew control for RXE channel D,

 

 

 

 

 

000 (default) applies to no delay added, ONE buffer

 

 

 

 

 

delay per step adjustment

 

 

 

 

 

 

 

 

 

 

 

 

[3]

Reserved

 

 

 

 

 

 

 

 

 

 

 

[2:0]

LVDS input skew control for RXE channel E,

 

 

 

 

 

000 (default) applies to no delay added, ONE buffer

 

 

 

 

 

delay per step adjustment towards Thold improvements

 

 

 

 

 

 

 

 

28d/1ch

R/W

None

[7:3]

Reserved

 

0000_0000

 

 

 

 

 

 

 

 

 

[2]

LVTTL output transition time control for CLK

 

 

 

 

 

0: Tr/Tf = 1.0ns (default)

 

 

 

 

 

 

1: Tr/Tf = 1.5ns

 

 

 

 

 

 

 

 

 

 

 

[1]

LVTTL output transition time control for RXE

 

 

 

 

 

0: Tr/Tf = 1.5ns (default)

 

 

 

 

 

 

1: Tr/Tf = 2.5ns

 

 

 

 

 

 

 

 

 

 

 

[0]

LVTTL output transition time control for RXO

 

 

 

 

 

0: Tr/Tf = 1.5ns (default)

 

 

 

 

 

 

1: Tr/Tf = 2.5ns

 

 

 

 

 

 

 

 

 

29d/1dh

R/W

None

[7:3]

Reserved

 

0000_0000

 

 

 

 

 

 

 

 

 

[2:1]

LVTTL output setup and hold time control

 

 

 

 

 

00: balanced setup and hold time (default)

 

 

 

 

 

01: setup time is increased from default position by 1UI

 

 

 

 

 

& hold time is reduced from default position by 1UI

 

 

 

 

 

10: setup time is decreased from default position by 1UI

 

 

 

 

 

& hold time is reduced from default position by 1UI

 

 

 

 

 

11: setup time is increased from default position by 2UI

 

 

 

 

 

& hold time is increased from default position by 2UI

 

 

 

 

 

 

 

 

 

 

 

[0]

LVTTL output PTO control

 

 

 

 

 

 

1: PTO disabled, all outputs setup time are only

 

 

 

 

 

controlled by contents of [2:1]

 

 

 

 

 

 

0: PTO enabled (default)

 

 

 

 

 

 

Group1: CLK to latch Data is re-assigned earlier by

 

 

 

 

 

0.5UI respect to the normal centered position if only

 

 

 

 

 

PTO option enabled; but PTO option and (Tsetup or

 

 

 

 

 

Thold) adjustment can co-exist

 

 

 

 

 

 

Group2: CLK to latch Data stays as the normal

 

 

 

 

 

centered position if only PTO option enabled; but PTO

 

 

 

 

 

option and (Tsetup or Thold) adjustment can co-exist

 

 

 

 

 

 

 

 

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Contents General Description FeaturesBlock Diagram Typical Application Diagram Functional DescriptionElectrical Characteristics Lvds Receiver DC SpecificationsAbsolute Maximum Ratings Note Recommended Operating ConditionsSymbol Parameter Conditions Min Typ Max Units Receiver Supply CurrentReceiver Switching Characteristics Symbol Parameter Condition Min Typ Max Units ReferenceTwo-Wire Serial Communication Interface AC Timing DiagramsWorst Case Test Pattern Receiver Phase Lock Loop Wake-up Time RFB Lvttl Level Programmable Strobe Select Receiver Input Tolerance and Sampling WindowReceiver Rsrc and Rhrc Output Setup/Hold Time PTO Enabled RegisterAddress 29d/1dh bit 21 = 00b20147115 Lvds Input Mapping Receiver Ritol Min and Max Pin Diagram DS90C3202 ReceiverDS90C3202 Pin Descriptions Pin No Pin Name Pin Type DescriptionDS90C3202 Pin Descriptions RXOA4 Lvttl O/P Two-Wire Serial Communication Interface Description Communicating with the DS90C3202 Control RegistersDS90C3202 Two-Wire Serial Interface Register Table ResetBit # Description Default Value AddressBit # Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver