National Products DS90C3202 manual Symbol Parameter Conditions Min Typ Max Units

Page 4

DS90C3202

Electrical Characteristics

(Continued)

 

 

 

 

 

 

Over recommended operating supply and temperature ranges unless otherwise specified.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

 

Conditions

 

Min

Typ

Max

Units

 

 

 

 

 

 

 

 

 

 

RECEIVER SUPPLY CURRENT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICCRW

Receiver Supply Current

 

CL = 8 pF,

f = 8 MHz

 

 

65

130

mA

 

Worst Case

 

Worst Case

 

 

 

 

 

 

 

(Figures 2, 4)

 

Pattern

 

 

 

 

 

 

 

f = 135 MHz

 

 

375

550

mA

 

 

 

Default Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Settings

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICCRG

Receiver Supply Current

 

CL = 8 pF,

f = 8 MHz

 

 

55

120

mA

 

Incremental Test Pattern

 

Worst Case

 

 

 

 

 

 

 

(Figures 3, 4)

 

Pattern

 

 

 

 

 

 

 

f = 135 MHz

 

 

245

400

mA

 

 

 

Default Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Settings

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICCRZ

Receiver Supply Current

 

PDWNB = Low

 

 

 

 

2

mA

 

Power Down

 

Receiver Outputs stay low

 

 

 

 

 

 

 

 

during Powerdown mode.

 

 

 

 

 

 

 

 

Default Register Settings

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for VDD = 3.3V and T A = +25˚C.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified.

Note 4: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.

Note 5: The incremental test pattern tests device power consumption for a “typical” LCD display pattern.

Note 6: Figures 2, 3 show a falling edge data strobe (RCLK OUT).

Note 7: Figure 8 show a rising edge data strobe (RCLK OUT).

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Contents Block Diagram FeaturesGeneral Description Typical Application Diagram Functional DescriptionElectrical Characteristics Lvds Receiver DC SpecificationsAbsolute Maximum Ratings Note Recommended Operating ConditionsSymbol Parameter Conditions Min Typ Max Units Receiver Supply CurrentReceiver Switching Characteristics Symbol Parameter Condition Min Typ Max Units ReferenceTwo-Wire Serial Communication Interface AC Timing DiagramsWorst Case Test Pattern Receiver Phase Lock Loop Wake-up Time RFB Lvttl Level Programmable Strobe Select Receiver Input Tolerance and Sampling WindowReceiver Rsrc and Rhrc Output Setup/Hold Time PTO Enabled RegisterAddress 29d/1dh bit 21 = 00b20147115 Lvds Input Mapping Receiver Ritol Min and Max Pin Diagram DS90C3202 ReceiverDS90C3202 Pin Descriptions Pin No Pin Name Pin Type DescriptionDS90C3202 Pin Descriptions RXOA4 Lvttl O/P Two-Wire Serial Communication Interface Description Communicating with the DS90C3202 Control RegistersDS90C3202 Two-Wire Serial Interface Register Table ResetBit # Description Default Value AddressBit # Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver