National Products DS90C3202 manual RegisterAddress 29d/1dh bit 21 = 00b

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DS90C3202

AC Timing Diagrams (Continued)

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RegisterAddress 29d/1dh bit [2:1] = 00b

FIGURE 12. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled

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FIGURE 13. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled

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Contents Block Diagram FeaturesGeneral Description Typical Application Diagram Functional DescriptionAbsolute Maximum Ratings Note Electrical CharacteristicsLvds Receiver DC Specifications Recommended Operating ConditionsSymbol Parameter Conditions Min Typ Max Units Receiver Supply CurrentReceiver Switching Characteristics Symbol Parameter Condition Min Typ Max Units ReferenceTwo-Wire Serial Communication Interface AC Timing Diagrams Worst Case Test Pattern Receiver Phase Lock Loop Wake-up Time RFB Lvttl Level Programmable Strobe Select Receiver Input Tolerance and Sampling WindowReceiver Rsrc and Rhrc Output Setup/Hold Time PTO Enabled RegisterAddress 29d/1dh bit 21 = 00b20147115 Lvds Input Mapping Receiver Ritol Min and Max Pin Diagram DS90C3202 ReceiverDS90C3202 Pin Descriptions Pin No Pin Name Pin Type DescriptionDS90C3202 Pin Descriptions RXOA4 Lvttl O/P Two-Wire Serial Communication Interface Description Communicating with the DS90C3202 Control RegistersBit # Description Default Value DS90C3202 Two-Wire Serial Interface Register TableReset AddressBit # Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver