National Products DS90C3202 manual RFB Lvttl Level Programmable Strobe Select

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AC Timing Diagrams (Continued)

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FIGURE 9. RFB: LVTTL Level Programmable Strobe Select

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RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12) Cable Skew — typically 10 ps–40 ps per foot, media dependent

Please see National’s AN-1217 for more details.

Note 11: Cycle-to-cycle jitter is less than 100 ps (worse case estimate).

Note 12: ISI is dependent on interconnect length; may be zero.

FIGURE 10. Receiver Input Tolerance and Sampling Window

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Register address 29d/1dh bit [2:1] = 00b

FIGURE 11. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Disabled

DS90C3202

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Contents Features Block DiagramGeneral Description Functional Description Typical Application DiagramLvds Receiver DC Specifications Electrical CharacteristicsAbsolute Maximum Ratings Note Recommended Operating ConditionsReceiver Supply Current Symbol Parameter Conditions Min Typ Max UnitsSymbol Parameter Condition Min Typ Max Units Reference Receiver Switching CharacteristicsAC Timing Diagrams Two-Wire Serial Communication InterfaceWorst Case Test Pattern Receiver Phase Lock Loop Wake-up Time Receiver Input Tolerance and Sampling Window RFB Lvttl Level Programmable Strobe SelectRegisterAddress 29d/1dh bit 21 = 00b Receiver Rsrc and Rhrc Output Setup/Hold Time PTO Enabled20147115 Lvds Input Mapping Receiver Ritol Min and Max DS90C3202 Receiver Pin DiagramPin No Pin Name Pin Type Description DS90C3202 Pin DescriptionsDS90C3202 Pin Descriptions RXOA4 Lvttl O/P Communicating with the DS90C3202 Control Registers Two-Wire Serial Communication Interface DescriptionReset DS90C3202 Two-Wire Serial Interface Register TableBit # Description Default Value AddressBit # Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver