National Products DS90C3202 manual Receiver Phase Lock Loop Wake-up Time

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DS90C3202

AC Timing Diagrams (Continued)

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FIGURE 6. Receiver Phase Lock Loop Wake-up Time

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FIGURE 7. Powerdown Delay

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FIGURE 8. Receiver Propagation Delay

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Contents General Description FeaturesBlock Diagram Typical Application Diagram Functional DescriptionElectrical Characteristics Lvds Receiver DC SpecificationsAbsolute Maximum Ratings Note Recommended Operating ConditionsSymbol Parameter Conditions Min Typ Max Units Receiver Supply CurrentReceiver Switching Characteristics Symbol Parameter Condition Min Typ Max Units ReferenceTwo-Wire Serial Communication Interface AC Timing DiagramsWorst Case Test Pattern Receiver Phase Lock Loop Wake-up Time RFB Lvttl Level Programmable Strobe Select Receiver Input Tolerance and Sampling WindowReceiver Rsrc and Rhrc Output Setup/Hold Time PTO Enabled RegisterAddress 29d/1dh bit 21 = 00b20147115 Lvds Input Mapping Receiver Ritol Min and Max Pin Diagram DS90C3202 ReceiverDS90C3202 Pin Descriptions Pin No Pin Name Pin Type DescriptionDS90C3202 Pin Descriptions RXOA4 Lvttl O/P Two-Wire Serial Communication Interface Description Communicating with the DS90C3202 Control RegistersDS90C3202 Two-Wire Serial Interface Register Table ResetBit # Description Default Value AddressBit # Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver