National Products manual DS90C3202 Two-Wire Serial Interface Register Table

Page 21

DS90C3202 Two-Wire Serial Interface Register Table (Continued)

Address

R/W

RESET

Bit #

Description

Default Value

 

 

 

 

 

 

30d/1eh

R/W

None

[7:5]

Reserved

0000_0000

 

 

 

 

 

 

 

 

 

[4]

I/O disable control for RXE channel A,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

 

 

 

[3]

I/O disable control for RXE channel B,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

 

 

 

[2]

I/O disable control for RXE channel C,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

 

 

 

[1]

I/O disable control for RXE channel D,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

 

 

 

[0]

I/O disable control for RXE channel E,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

31d/1fh

R/W

None

[7:6]

11; LVTTL Outputs available as long as "NO CLK" is at

0000_0000

 

 

 

 

HIGH regardless PLL lock or not

 

 

 

 

 

10; LVTTL Outputs available after 1K of CLK cycles

 

 

 

 

 

detected & PLL generated strobes are within 0.5UI

 

 

 

 

 

respect to REFCLK

 

 

 

 

 

01; LVTLL Outputs available after 2K of CLK cycles

 

 

 

 

 

detected

 

 

 

 

 

00: default ; LVTTL Outputs available after 1K of CLK

 

 

 

 

 

cycles detected

 

 

 

 

 

 

 

 

 

 

[5]

0: default; to select the size of wait counter between 1K

 

 

 

 

 

or 2K, default is 1K

 

 

 

 

 

 

 

 

 

 

[4]

I/O disable control for RXO channel A,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

 

 

 

[3]

I/O disable control for RXO channel B,

 

 

 

 

 

1 disable, 0: enable (default)

 

 

 

 

 

 

 

 

 

 

[2]

I/O disable control for RXO channel C,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

 

 

 

[1]

I/O disable control for RXO channel D,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

 

 

 

[0]

I/O disable control for RXO channel E,

 

 

 

 

 

1: disable, 0: enable (default)

 

 

 

 

 

 

 

Note 13: Registers with RESET designated with “None” requires device to be power cycled to reset register values to their default state.

DS90C3202

21

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Contents Features Block DiagramGeneral Description Functional Description Typical Application DiagramLvds Receiver DC Specifications Electrical CharacteristicsAbsolute Maximum Ratings Note Recommended Operating ConditionsReceiver Supply Current Symbol Parameter Conditions Min Typ Max UnitsSymbol Parameter Condition Min Typ Max Units Reference Receiver Switching CharacteristicsAC Timing Diagrams Two-Wire Serial Communication InterfaceWorst Case Test Pattern Receiver Phase Lock Loop Wake-up Time Receiver Input Tolerance and Sampling Window RFB Lvttl Level Programmable Strobe SelectRegisterAddress 29d/1dh bit 21 = 00b Receiver Rsrc and Rhrc Output Setup/Hold Time PTO Enabled20147115 Lvds Input Mapping Receiver Ritol Min and Max DS90C3202 Receiver Pin DiagramPin No Pin Name Pin Type Description DS90C3202 Pin DescriptionsDS90C3202 Pin Descriptions RXOA4 Lvttl O/P Communicating with the DS90C3202 Control Registers Two-Wire Serial Communication Interface DescriptionReset DS90C3202 Two-Wire Serial Interface Register TableBit # Description Default Value AddressBit # Description DS90C3202 Two-Wire Serial Interface Register Table DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver