Texas Instruments TMS320C6455 specification

Using the DDR2 Memory Controller

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Figure 16. Connecting to Two 16-Bit DDR2 SDRAM Devices

DDR2CLKOUT

DDR2CLKOUT

DSDCKE

DDR2DCE0

Memory

Controller DSDWE

DSDRAS

DSDCAS

DSDDQM0

DSDDQM1

DSDDQS0

DSDDQS0

DSDDQS1

DSDDQS1

DBA[2:0]

DEA[13:0]

DED[15:0]

DSDDQM2

DSDDQM3

DSDDQS2

DSDDQS2

DSDDQS3

DSDDQS3

DED[31:16]

ODT0

ODT1

DDRSLRATE VDD

DSDDQGATE0(A)

DSDDQGATE1(A)

DSDDQGATE2(A)

DSDDQGATE3(A)

VREF

CK

CK

CKE

									DDR2
	CS								DDR2
	CS								Memory

	WE
	WE								x16-bit
									x16-bit
	RAS

	CAS

	LDM

	UDM
	LDQS

	LDQS
	UDQS

	UDQS
	BA[2:0]
	A[12:0]
	DQ[15:0]
	ODT
	VREF
	CK

	CK
	CKE
									DDR2
	CS								DDR2
	CS								Memory

	WE
	WE								x16-bit
									x16-bit
	RAS

	CAS

	LDM

	UDM
	LDQS

	LDQS
	UDQS

	UDQS
	BA[2:0]
	A[12:0]
	DQ[15:0]
	ODT
	VREF

AThese pins are used as a timing reference during memory reads. For routing rules, see the device-specific data manual.

32	C6455/C6454 DDR2 Memory Controller	SPRU970G – December 2005 – Revised June 2011
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Texas Instruments TMS320C6455 manual Connecting to Two 16-Bit DDR2 Sdram Devices

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control DDR2 Memory Controller Signal Descriptions Pin Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Refresh Mode Refresh Command Actv Command Activation Actv Dcab Command Deactivation Dcab and Deac Deac Command Read Command DDR2 Read Command Write WRT Command Memory Width, Byte Alignment, and EndiannessAddressable Memory Ranges Address Type Generated by DDR2 Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description DDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced Concept Command Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level Description Self-Refresh Mode Reset ConsiderationsDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field 11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 Sdram Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Field DDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration SDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description Register Description DDR2 Memory Controller RegistersOffset Bit Field Value Description Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions DDR2 Memory Controller Status Register Dmcstat Ifrdy Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC Trrd Using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Txsnr Txsrd Trtp Tcke Prioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History Products Applications DSPRfid TI E2E Community Home