Texas Instruments TMS320C6455 Interrupt Support, Edma Event Support, Emulation Considerations

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2.11.2DDR2 SDRAM Initialization After Reset

After a hard or a soft reset, the DDR2 memory controller will automatically start the initialization sequence. The DDR2 memory controller will use the default values in the SDRAM timing 1 and timing 2 registers and the SDRAM configuration register to configure the mode registers of the DDR2 SDRAM device(s). Note that since a soft reset does not reset the DDR2 memory controller registers, an initialization sequence started by a soft reset would use the register values from a previous configuration.

2.11.3DDR2 SDRAM Initialization After Register Configuration

The initialization sequence can also be initiated by performing a write to the two least-significant bytes in the SDRAM configuration register (SDCFG). Using this approach, data and commands stored in the DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands are completed before starting the initialization sequence.

Perform the following steps to start the initialization sequence:

1.Set the BOOT_UNLOCK bit in the SDRAM configuration register (SDCFG).

2.Write a 0 to the BOOT_UNLOCK bit along with the desired value for the DDR_DRIVE bit.

3.Program the rest of the SDCFG to the desired value with the TIMUNLOCK bit set (unlocked).

4.Program the SDRAM timing 1 register (SDTIM1) and SDRAM timing register 2 (SDTIM2) with the value needed to meet the DDR2 SDRAM device timings.

5.Program the REFRESH_RATE bits in the SDRAM refresh control register (SDRFC) to a value that meets the refresh requirements of the DDR2 SDRAM device.

6.Program SDCFG with the desired value and the TIMUNLOCK bit cleared (locked).

7.Program the read latency (RL) bit in the DDR2 memory controller control register (DMCCTL) to the desired value.

2.12Interrupt Support

The DDR2 memory controller does not generate any interrupts.

2.13 EDMA Event Support

The DDR2 memory controller is a DMA slave peripheral and therefore does not generate EDMA events. Data read and write requests may be made directly by masters including the EDMA controller.

2.14 Emulation Considerations

The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access to external memory.

30	C6455/C6454 DDR2 Memory Controller	SPRU970G – December 2005 – Revised June 2011
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