Revision History | Texas Instruments TMS320C6455 guide

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Revision History

Revision History

This revision history highlights the technical changes made to the document in this revision.

See	Additions/Modifications/Deletions

Table 1	Modified Description for DEODT[1:0] Pins
Table 10	Modified Descriptions for Bits 6 and 2
Figure 16	Modified ODT pins in figure
Figure 17	Modified ODT pins in figure
Figure 18	Modified ODT pins in figure

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

SPRU970G – December 2005 – Revised June 2011	Revision History	49
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Copyright © 2005–2011, Texas Instruments Incorporated

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Texas Instruments TMS320C6455 manual Revision History

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Refresh Command Refresh Mode Activation Actv Actv Command Deactivation Dcab and Deac Dcab Command Deac Command DDR2 Read Command Read Command Memory Width, Byte Alignment, and Endianness Write WRT CommandAddressable Memory Ranges Address Type Generated by DDR2 Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Considerations Self-Refresh ModeDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field 11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Field Sdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration Dmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description Offset DDR2 Memory Controller RegistersRegister Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrBit Field Value Description Ifrdy DDR2 Memory Controller Status Register Dmcstat Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC Trrd Using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Txsnr Txsrd Trtp Tcke Burst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History DSP Products ApplicationsRfid TI E2E Community Home