Using this formula | Texas Instruments TMS320C6455 manual

www.ti.comDDR2 Memory Controller Registers

	Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued)

Bit	Field	Value	Description

5-3	T_RRD		These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to an
			activate command in a different bank, minus 1. The value for these bits can be derived from the trrd
			AC timing parameter in the DDR2 memory section of the device-specific data manual. Calculate
			using this formula:
			T_RRD = (trrd/DDR2CLKOUT) - 1
			When connecting to an 8-bank DDR2 SDRAM, this field must be equal to:
			T_RRD = ((4trrd + 2tck) / (4*tck)) - 1

2	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

1-0	T_WTR		These bits specify the minimum number of DDR2CLKOUT cycles from the last write to a read
			command, minus 1. The value for these bits can be derived from the twtr AC timing parameter in the
			DDR2 memory section of the device-specific data manual. Calculate using this formula:
			T_WTR = (twtr/DDR2CLKOUT) - 1

SPRU970G – December 2005 – Revised June 2011	C6455/C6454 DDR2 Memory Controller	45
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Texas Instruments TMS320C6455 manual Using this formula

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Refresh Command Refresh Mode Activation Actv Actv Command Deactivation Dcab and Deac Dcab Command Deac Command DDR2 Read Command Read Command Memory Width, Byte Alignment, and Endianness Write WRT CommandAddressable Memory Ranges Address Type Generated by DDR2 Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Considerations Self-Refresh ModeDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field 11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Field Sdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration Dmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description DDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description Ifrdy DDR2 Memory Controller Status Register Dmcstat Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC Trrd Using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Txsnr Txsrd Trtp Tcke Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History DSP Products ApplicationsRfid TI E2E Community Home