Contents | Texas Instruments TMS320C6455 specs

Contents

Preface			7
1	Introduction		9
	1.1	Purpose of the Peripheral	9
	1.2	Features	9
	1.3	Functional Block Diagram	9
	1.4	Industry Standard(s) Compliance Statement	10
2	Peripheral Architecture		11
	2.1	Clock Control	11
	2.2	Memory Map	11
	2.3	Signal Descriptions	11
	2.4	Protocol Description(s)	13
	2.5	Memory Width, Byte Alignment, and Endianness	20
	2.6	Address Mapping	21
	2.7	DDR2 Memory Controller Interface	24
	2.8	Refresh Scheduling	27
	2.9	Self-Refresh Mode	28
	2.10	Reset Considerations	28
	2.11	DDR2 SDRAM Memory Initialization	28
	2.12	Interrupt Support	30
	2.13	EDMA Event Support	30
	2.14	Emulation Considerations	30
3	Using the DDR2 Memory Controller		31
	3.1	Connecting the DDR2 Memory Controller to DDR2 SDRAM	31
	3.2	Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications	35
4	DDR2 Memory Controller Registers		38
	4.1	Module ID and Revision Register (MIDR)	39
	4.2	DDR2 Memory Controller Status Register (DMCSTAT)	40
	4.3	SDRAM Configuration Register (SDCFG)	41
	4.4	SDRAM Refresh Control Register (SDRFC)	43
	4.5	SDRAM Timing 1 Register (SDTIM1)	44
	4.6	SDRAM Timing 2 Register (SDTIM2)	46
	4.7	Burst Priority Register (BPRIO)	47
	4.8	DDR2 Memory Controller Control Register (DMCCTL)	48
Revision History			49

SPRU970G – December 2005 – Revised June 2011	Table of Contents	3
Submit Documentation Feedback

Copyright © 2005–2011, Texas Instruments Incorporated

Image 3

Texas Instruments TMS320C6455 manual Contents

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Refresh Command Refresh Mode Activation Actv Actv Command Deactivation Dcab and Deac Dcab Command Deac Command DDR2 Read Command Read Command Address Type Generated by DDR2 Write WRT CommandMemory Width, Byte Alignment, and Endianness Addressable Memory Ranges Ibank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency Levels DDR2 Memory Controller Reset Effect Initiated by Self-Refresh ModeReset Considerations Device and DDR2 Memory Controller Reset Relationship Mode Register Field 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 Configuration Edma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Field Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register Sdrfc SDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2 Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet Parameter DDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description Ifrdy DDR2 Memory Controller Status Register Dmcstat Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Tras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWR Using this formula Txsrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt Txsnr Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History TI E2E Community Home Products ApplicationsDSP Rfid